JPS58114795U - timer device - Google Patents

timer device

Info

Publication number
JPS58114795U
JPS58114795U JP1216582U JP1216582U JPS58114795U JP S58114795 U JPS58114795 U JP S58114795U JP 1216582 U JP1216582 U JP 1216582U JP 1216582 U JP1216582 U JP 1216582U JP S58114795 U JPS58114795 U JP S58114795U
Authority
JP
Japan
Prior art keywords
time
memory
signal
clock
timer device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1216582U
Other languages
Japanese (ja)
Inventor
満 吉田
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP1216582U priority Critical patent/JPS58114795U/en
Publication of JPS58114795U publication Critical patent/JPS58114795U/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は本考案による一実施例を示すブロック図である。 1・・・刻時計数部、2・・・発振回路、3・・・予約
キースイッチ、4・・・第1メモリ、5・・・加算回路
、6・・・第2メモリ、71,7□・・・比較部。
The figure is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Clock counter, 2... Oscillation circuit, 3... Reserved key switch, 4... First memory, 5... Addition circuit, 6... Second memory, 71, 7 □・・・Comparison section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基本クロックに基いて実時間を計数する刻時計数部と、
該刻時計数部の時刻信号を取り出すスイッチと、取り出
された時刻信号を所定時間後のスタート時刻として記憶
する第1メモリと、該第1メモリの記憶時刻に所定時間
を加算して終了時刻を設定する第2メモリと、第1及び
第2メモリの各設定時刻と刻時計数部の計数値を比較し
てタイマーオン及びオフ信号を形成する比較部とを備え
てなるタイマー装置。  ・
a clock counter that counts real time based on a basic clock;
a switch for taking out the time signal of the clock section; a first memory for storing the taken out time signal as a start time after a predetermined time; and a end time by adding a predetermined time to the time stored in the first memory. A timer device comprising: a second memory for setting time; and a comparison section for comparing each set time in the first and second memories with the count value of a clock counter to form a timer on and off signal.・
JP1216582U 1982-01-29 1982-01-29 timer device Pending JPS58114795U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1216582U JPS58114795U (en) 1982-01-29 1982-01-29 timer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1216582U JPS58114795U (en) 1982-01-29 1982-01-29 timer device

Publications (1)

Publication Number Publication Date
JPS58114795U true JPS58114795U (en) 1983-08-05

Family

ID=30024753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1216582U Pending JPS58114795U (en) 1982-01-29 1982-01-29 timer device

Country Status (1)

Country Link
JP (1) JPS58114795U (en)

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