JPS58114252A - Data processor - Google Patents

Abstract

PURPOSE:To execute retrial of an instruction without dropping the performance, by saving a data each time when reading out the data from a main storage device, and saving the original contents only once when writing in a register. CONSTITUTION:An information processor provides a main storage device 1 of large capacity for storing an instruction and an operand data, a buffer storage device 2 of a high speed and comparatively small capacity, an instruction controller 3 for decoding the instruction and executing an advance control of the instruction, an execution controller 4 for executing the instruction, a saving and recovery controller 5, and a saving device 6 for saving a normal state in the course of executing the instruction. After a check point has been set, when reading out a data from the main storage device 1, the data is saved in the saving device 6 each time, and when writing in registers 41-44, the original contents are saved in the saving device 6 only once, and when an abnormal state has been detected, the saved contents are reset to the main storage device 1 or the registers 41-44.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing apparatus using a retry method, and more specifically, to a data processing apparatus that re-executes a plurality of instructions in the event of an intermittent hardware failure.

The issue of increasing the reliability of information processing systems has always been an important issue in the design of information processing equipment. In the design of information processing systems, there are two types of design methods: one that eliminates the factors that cause errors to occur, and the other that minimizes the impact of errors even if they occur. One of the latter design methods includes a retry technique in which an error p is detected during processing by the processing means, and when it is too late to continue the processing, re-execute the one-dead processing once or multiple times. This retry is a technique that has become important in recent information processing systems because many WAp are temporary and many WAp can be saved by retrying.

However, retrying cannot be done indiscriminately when an error occurs; it is only possible if the hardware state 11 can be returned to the state before the processing was executed. Therefore, in retry design, the rate at which retries can be performed, that is, the ability to improve the retry possibility rate, is important.

Conventionally, as a means to improve the retry possibility rate, there has been a method of saving necessary registers or memory contents before starting processing of an instruction, or a method of saving the contents of necessary registers or memory before starting processing of an instruction, or a method of changing the state of the hardware to
A method such as doing it as late as possible during the cycle should be adopted. However, conventional means of improving the retryability rate are limited to only one instruction, and there are inherent limitations. For WAp,
Retry is required because the hardware cannot be restored to its original state! I have the disadvantage of not being able to vagina.

As a way to solve the above-mentioned drawbacks, a technique has recently been proposed that allows retrying multiple instructions.

Patent Publication No. 3-111111, Name List of Invention Data Processing System IK The system shown saves the original contents before writing to the main memory, and when llb occurs, returns to the original state with the saved contents and restarts. This is a trial version and has superior technology that eliminates the drawbacks of conventional technology. The above patent allows for the use of the store-in-buffer storage (referred to as small capacity high speed storage in the above patent) feature to retire the original contents of main memory. That is, IIK uses a store-in buffer method in which data is written to the main memory without fail, in which the original data in the main memory is taken into the buffer memory and then written only to the buffer memory.

Therefore, the above-mentioned patent is applicable only to an information processing device having a store-in buffer type buffer storage device, and is applicable only to an information processing device having a store-in buffer type buffer storage device. For example, it has a drawback that it cannot be applied to an information processing apparatus that employs a method in which data is written to a buffer storage device and a main memory device, and if it is not loaded, it is written only to the main memory device.

Furthermore, the above-mentioned patent has the disadvantage that it cannot be applied because the information processing apparatus Kti, which does not have a buffer storage device, suffers from a significant drop in performance.

On the other hand, as explained earlier, in the store-in buffer method, there is a mismatch between the contents of the buffer storage device and the contents of the main storage device, so when a permanent failure occurs in the buffer storage device, the buffer storage device is It has another drawback in terms of reliability, as it is not possible to disconnect part or all of it for degenerate operation, resulting in system failure. On the other hand, with the store-through type, the contents of the main memory are always partially stored on the buffer storage, so even if there is a fixed failure in the buffer storage, the system will not go down and the storage system will be overheated. [Tshwa method] has superior advantages in terms of authenticity.

An object of the present invention is to eliminate the above-mentioned drawbacks from data by saving the original content when reading it from the main memory, instead of saving the original content when writing to the main memory. The purpose of this invention is to provide a processing device.

More specifically, it is an object of the present invention to provide a data processing device that enables retrying with a high retryability rate over a plurality of instructions even in an information processing device having a buffer storage device of not only a store-in buffer type but also a store-through type. Another object of the present invention is to provide a data processing device that allows retrying without degrading performance even in an information processing device that does not have a buffer storage device.

To achieve the above object, a data unit layer device according to the present invention includes a storage device for storing instructions and operand data, an instruction address counter and an instruction decoder, an instruction control device connected to the storage device, and an instruction control device connected to the storage device; an execution control device that is responsive to the control device and that is connected to the storage device to read or write operand data in the storage device and includes a plurality of registers necessary for executing instructions;
A normal state indicating device that is provided in relation to the storage device, the instruction control device, and the execution control device, and that indicates a plurality of normal states during processing of an instruction, and an abnormal state detection device that detects a plurality of abnormal states. a normal state instruction and abnormal state detection device including a normal state instruction and abnormal state detection device; a save storage device having a transfer path between the storage device; a save register having a transfer path between a plurality of registers included in the execution control device; An arbitrary normal state is indicated by the save instruction address counter having a transfer path between the instruction address counter and the normal state indicating device, and execution of the last instruction being decoded at the time of the instruction is completed. In response to this, a checkpoint device transfers the contents of the instruction address counter indicating an instruction next to the last instruction to the save instruction address counter, and after the above instruction, the contents of the instruction address counter are transferred from the storage device to A memory evacuation control device that transfers this operand data to the evacuation storage device when reading data; and a memory evacuation control device that transfers this operand data to the evacuation storage device when reading data; a register save control device that transfers the contents of the save instruction address counter to the save register; and a register save control device that transfers the contents of the save instruction address counter to the instruction address counter in response to any abnormal condition being detected by the abnormality register. a recovery control device that also reversely transfers the contents of the save register to a register included in the concentration control device and reversely transfers the contents of the save memory to the predistribution storage device; until the operation of the recovery device is completed in response to any abnormal condition being detected by the detection device or in response to any normal condition being indicated by the normal condition indicating device. and a device for inhibiting the operation of the instruction control device O until the depth of the last instruction that has been decoded is completed and the operation of the checkpoint device is completed.

In the present invention, when reading data from the main memory,
If you save the m data and write it to the register, you can save the original content only once, and even if the data on the main memory or the register is written afterwards, the original content will be restored automatically. It is based on the principle that The present principle will be explained with reference to the drawings.

FIG. 1 is a diagram showing two instruction sequences, in which registers t-R1, R2, ..., operand data on the main memory are transferred to OPI, OF2, . ..., and a1~
a3. i*1 to bs each indicate one instruction. FIGS. 1(a) and 1(b) also show operand data OP1, OF2, . OF2. OF2 each has a value of 112°3.4, registers R1, R2, R3
, R4 have values of 1, 2, and 3.4, respectively, and the contents of each operand data and each register at the time of execution of each instruction are shown. Referring to FIG. 1 C&), each time the operand data is read in the execution of each instruction, the operand data is saved, that is, OPl (value l) for instruction a1,
Then, if we save OPl (value 3) and 0P4 (value 4) and 0P3 (value 7) for instruction a3, we can save operand data when an abnormal condition is detected in the instruction m5Dl [line]. That is, when 0P3 (value 7) → 0P4 (value 4) → 0Ps (value 1) - +0P1 (value 1) is written to the main memory, the operand data - 0PI, OF! .

OF2 has values of 1 and 3.4, respectively, indicating that it can be re-executed from the instruction a1.
P2 is re-executed without being returned to the value 2, but there is no problem in operation.This is because if the operand data is simply written without being read, the original contents of the write command must be saved and the attack (even if it is dangerous). It shows.

Referring to FIG. 1 (nil), when writing to the register in the execution of each instruction - only the vertical is saved, that is, in the instruction b1, R2
(If R3 (value 3) is saved in the instruction b2, it can be saved when an abnormal condition is detected during the execution of the instruction bs, and restored with the contents of the register, that is, if R2°R3 is returned to the value !, 3, the instruction b1 1. I will explain Soo Hara using two examples with reference to the drawings that show that re-execution is possible from 1 to 4. The good news is obvious.

Next, the present invention will be explained with reference to the drawings showing the back cover.

FIG. 2 illustrates an information processing apparatus using the present invention, which includes a large-capacity main storage device 1 for storing instructions and operand data, and one high-speed or relatively small-capacity buffer storage device 2.
, an instruction control device 3 that decodes instructions and performs preemption control of instructions, an execution control device 4 that executes instructions, an evacuation and recovery control device 5 that occupies the main position of the present invention, and a normal state during instruction execution. and an evacuation device for evacuation.

The buffer storage device 2 includes a storage unit 22 and a pointer) IJ 21, is connected to the main storage device 1 through data [1 &#1b, and is connected to the instruction control device 3 and the execution control device 4 and data 112.
m, connected by 2b.

The instruction control device 3 has an instruction buffer 31 consisting of three entries for instruction prefetch p, an instruction counter 3S indicating the location in the main memory device 1 of the next instruction to be executed 111111h, and an instruction counter 3S (not shown in the figure). It includes an instruction decoder for decoding instructions, and is connected to the execution control device 4 via data ILSm and T&.

Execution control device 4Fi 16 general-purpose registers 41 used for various operations, 8 base registers 42 used for addresses when accessing operand data, 4 scientific operation registers 43 for scientific operations, It includes a status register 44 that reflects the condition code of the multi-operation result with exceptions masked, and a plurality of arithmetic units that can operate in parallel, although not shown in the figure. Each arithmetic unit processes operand data existing in each of the registers 41 to 44 and the main storage device 1 in accordance with the decoded instructions transferred by data IHa and 7m.

A main memory evacuation buffer 6@ which performs evacuation and restoration of data via the evacuation device 6Fi buffer storage 2t or main memory device 1 and data #5, a, and S(l),
General-purpose register 41 and data 51a of execution control device 4,
A general-purpose save register 61 consisting of 16 entries and a base register 42 for transferring data via Ilb.
and a base save register 62 consisting of eight entries for saving and restoring data via data lines 52m and 12b;
Scientific operation register 43 and data line 53 m, 53
A scientific operation save register @3 consisting of 4 entries and a status register 4 for saving and restoring data via
4 and data lines 54&, 54b, and a status save register 64 for saving and recovering data; and an instruction counter save register 65 for saving and recovering data via the instruction counter 3s and data 1155a and SSb of the instruction control device 3. A save register 111. @2. it
Each entry of s, li4 has save bits 11, 1121.11$1., which indicate whether the contents have been saved or not. 64
1, and the evacuation device 6 includes a main memory evacuation buffer 60.
and a save buffer pointer 66 pointing to the entry in the main memory save buffer 60 when accessing the address l.
! 6 Indicate with @a. The save buffer pointer 66 has signals I16.b, .lig, and $@d as input signals,
The contents of the evacuation buffer pointer 66 are cleared by the signal *seb, and the contents are incremented by +1 or -1 by the signal lines 66C and 6.d.

The save/recovery control device S includes the instruction counter 3S in the instruction control device 13 or the registers 41 to 41 in the execution control device 4.
44 to the saving device 6, a recovery instruction signal @ssb that instructs the instruction counter 3s or each register 41 to 44 to recover from the saving device 6, and an execution control line An execution completion signal II4 from the execution control device 4 indicating that execution of all instruction execution sequences held by the device 4 has been completed! Im, a main memory read signal [ii4@m, which notifies that the execution control device 4 has read data from the main memory 1, and a general-purpose register J#41.
．． Pace register 42. A general-purpose register write signal 1141m, a base regime write signal set 42a, and a scientific operation register write signal set 43m notify that writing can be performed to the scientific operation register 4s and the status register 44.
and status register write signal -44m,
Circuit SO~Il, BT, OR circuit port, gate So
f.

! i11,521,531,541,551&! 57
0°571.572,573,574. r175.

The ANDlal path 50 has the save instruction signal line ■j and the main memory continuous output signal line 40m as inputs, and has the signal line 50C as an output, and the gate 501 uses the signal line Sot as a gate signal to control the data line Set.

AND circuits 51, 52, 53, 54r! It has a save instruction signal line 5/a as one input, and each register write signal 11411142 & 4 as the other input.
3 m and 44 m, and have signal lines 51c, S2o, SSc, and S4c as outputs, respectively. gate 51
1,521,531,541 are signal lines 51s, 52c,
Data line 5 l a with SS@ and S4o as gate signals
, S 2 a, S S a, 541. The AND circuit 55 receives the save instruction signal line Sea and the execution completion signal 1i145a as inputs, and receives the signal line 5! I@ as an output, and the signal @See is sent to each save register 61 . If, IIS, li4 save bit fill,
Ill, instruct Talia of 111,841. gate 5
s1 is the signal line S! Data line 55m with @ as gate signal
control.

The system ND circuit S7U recovery instruction signal *ssb and the execution completion signal line 45m from the execution control device 4 are input, and the signal line s7C
has as output. day) 570°571.572,5
73,574.57SU signal line 57c as a gate signal and data lines Sob, 51b, S2b, 53b,
Controls S4b and 55b. The OR circuit 56 outputs the save instruction signal line Sla and the recovery instruction signal 1! It has S8b as an input and the signal line Se@ as an output.

Furthermore, in FIG. 2, the data lines 3a and 1b for transferring decoded instructions from the instruction control device 3 are
It includes an inhibition circuit 7 which is controlled by.

FIG. 3 shows a general-purpose register 410 of the execution control device 4 in FIG.
FIG. 3 is a diagram showing peripheral circuits in detail. Third cause KFi A general-purpose write data register 81 that holds the data written to the general-purpose register 41, a general-purpose read data register 92 that holds the read data from the general-purpose register 41, and the general-purpose register 41 at the time of writing and reading. General purpose write address register 83 and general purpose read address register 94 indicating entries of
and data ## to transfer write data and read data.
91m and 92m, addresses @SS Hatake and 14m that transfer the entry address in the general-purpose register 41 during writing and reading, and writing to the general-purpose register 41 (%l
Signal indicating whether to read or read (value %OI)! 95m is shown. Figure 3 shows that when the signal line 85m is %11, the output of the general-purpose write address register s3 is given to the general-purpose register 41, and when the signal line 85m is %61, it is inhibited. A selector S6 is shown that transfers the write address indicating the entry in the general-purpose register 41 at the time to the general-purpose read data register s2.

Before explaining this embodiment with the above configuration, the operation of the buffer storage device 2 will be explained.The buffer storage device 2 used in this embodiment employs a store-through type. Store through 5eFi main memory 1 or instruction or operand data - memory section 22 of buffer memory 2 during reading
After reading the read data, it is transferred to the instruction control device 3 or the execution control device 4, and then when reading out the data, it is read out from the storage section 22 of the buffer storage device 2 without removing it from the main storage device 1. When writing, if the relevant data exists in the storage unit 22 of the buffer storage [12], it will be written to both the storage unit 22 and the main storage device 1, and if the relevant data is not in the storage unit 22, it will be written to the main storage device 1. This is a method of writing only to the The store-through method is a well-known technique in contrast to the store-in buffer method.

Next, an outline of instruction retry before multiple instructions will be explained with reference to FIG. Command retry of multiple instructions according to the present invention is achieved by: - setting a known normal state of the information processing device shown in FIG. It's about being able to help yourself.

The time point at which a known normal state is set is hereinafter referred to as a checkpoint. Although the checkpoint is not shown in the figure, it is set as follows, and is notified to the evacuation recovery control device 5 via the evacuation instruction signal line ■1. be done.

(1. When a startup command is executed for an external device or when an interrupt from an external device is rarely received) For example, the external device includes a peripheral device, which is not shown in FIG. When a startup command is attached to an external device and executed, the data in the main storage device 1 is likely to be changed by the external device, and it may not be possible to return to the previously set checkpoint state. Furthermore, since interrupts from external devices occur asynchronously with instruction execution, operation may not be guaranteed even if the instruction is retried from a previous checkpoint. Therefore, in this case, it is necessary to set a new checkpoint.

(2. When the main memory save buffer 60 is full) The main memory save buffer 60 has only 256 entries in this embodiment. Therefore, it is necessary to save data in the main memory 1 beyond this buffer, rounding up to 111, and setting a checkpoint every f#.

(3. The instruction control device 3 decodes the preset value O instructions and runs) Checkpoint settings due to the causes of ill and 1fll+ described above occur only rarely, and a large number of alloys are set between checkpoints. Once executed, it requires a significant amount of time to recover and retry. To eliminate this problem, a certain number of instructions are decoded from the previous checkpoint setting and a new checkpoint is set at runtime.

The point at which the normal state set at the checkpoint is restored, that is, a retry is required, is when the following abnormality occurs, and the evacuation and recovery control device s is notified by the recovery instruction signal ill/b. .

(L: When a machine check is detected) If a machine check may occur due to various failures, the system logs out the failure information necessary to identify the failure location, reboots the system, and then returns to the normal state. This is because most of the failures are intermittent and there is a high probability that they will be remedied by retrying.

(2, The supplied instruction is rewritten at 9 o'clock) The instruction control device f3 preemptively fetches the instruction p7, writes the preceding instruction to the main memory 1, rewrites the instruction, and rewrites the instruction at run time. Instructions and sex are required.

(3. Detecting and running the estimated line of response to activation of peripheral device) When executing a startup command to the Liube device, the response from the peripheral device is estimated and subsequent commands are pre-emptively executed. If the actual response to the activation command differs from the estimated value, it is necessary to re-execute from the checkpoint at the time of execution of the activation command, as described above.

The details of this embodiment will be explained with reference to FIGS. 2 and 3 again. When a checkpoint is set, evacuation instruction signal line 5
Eat-%1' and evacuation recovery control device! 5 will be notified. The evacuation recovery control system @S sends % to the signal line Sec via the OR circuit 56 when the evacuation instruction line 01 51ia becomes slg.
11, and the prohibition circuit 1 acts to prohibit the supply of decoded instructions from the instruction control device 3. When the supply of subsequent instructions is stopped, the plurality of arithmetic units (not shown in the figure) in the execution control device 4 operate to complete the operations according to the previously supplied instructions, and when all operations are completed, Set the execution completion signal @45m to 111,
The evacuation and recovery control device gt5 is notified again. The ND circuit 55 of the evacuation 1 return control cover S receives three inputs at this point, namely the evacuation instruction signal line 5@a and the execution completion signal @45.
Since m is 111, the output signal line 55s is 11I.
shall be. When the signal 1155g is 'l' and e, game) 55
1 transfers the contents of the instruction counter 3s to the instruction counter save register Ii5 of the save device 6 via the data line 55m, and also transfers the contents of the instruction counter 3s to the instruction counter save register Ii5 of the save device 61 and the base save register 62. The save bits 611, 621, 631 of each entry of the scientific operation save register 63 are cleared, the save bit 641 of the status register 64 is cleared, and the save buffer pointer 66 is cleared.

The checkpoint setting is completed when the above operation by %11K of signal @55C is performed. When the checkpoint setting is completed, the evacuation instruction signal line 56m and the execution completion signal line 45m both become %01, the prohibition state of the instruction supply of the prohibition circuit 1 is canceled, and the instruction control device 3 again decodes the execution control device 4-\decode. The supplied instructions are started to be supplied.

Next, a description will be given of an information storage operation for enabling return to a checkpoint when an abnormal state is detected. When the execution control device 4 instructs the main memory device 1 to perform a read operation, the main memory read signal line 40m and the evacuation instruction signal 156m are set to 11.
1 and notifies the evacuation and recovery control device S. The AND circuit 50 of the save and recovery control aSS has two input signal lines 40a.
, since S@a is 111, the output signal line 50c is set to 1.
1I and opens the gate 501. The read data from the semi-storage device 1 is performed via the buffer storage device 2 as already explained, and is transferred to the execution control device 4 via the data line 2a, and is also transferred to the main storage device. It is also sent to the data line Set with the subsequent address information for 1 added thereto. data! ms@
Since the gate 501 is open, the read data and read address information on a are stored in the entry indicated by the save buffer pointer 1i6 of the main memory save buffer 60 in the save device 6. The contents of the save buffer pointer 66 are incremented by 1 by the signal line @6C instruction.

Before writing to the general-purpose register 41, the execution control device 4 uses the general-purpose register write signal line 41m and the save instruction signal line 5e.
Set it to at%II. AND circuit s of evacuation and recovery control device 2
1 is the %lI of these three signals 1i141"esfJ'&
In response to the output signal line 51ct%lI, the gate 51
Open 1. Referring now to FIG. 3, general purpose register 4
When writing 10, the signal line 15m becomes %Ig, and the address information indicating the internal operation/try of the general-purpose register 41 is transferred to the general-purpose write address register 3 via the address line 113m. At this time, the signal line @sa becomes %1111C1, □V'l fi S @Eyo, A4. 3°. 3
The address information of ゜ is also transferred to the general-purpose read address register 4, the entry contents of the general-purpose register 41 indicated by the general-purpose read address register s4 are sent to the data line S1m, and after -t, the general-purpose read address register s3 is transferred to the general-purpose register 41. A write operation to register 41 is performed. Referring again to FIG. 2, the gate 511 is in an open state, and the original content of the song written to the ninth general-purpose register 41 is transferred to the save device 6 and stored in the corresponding entry of the general-purpose save register 61. Although not shown in the figure, the save bit 611 of the entry is set to %11 at the same time. Note that if the save bit of the roar entry is already %II, storage to the general purpose save register 61 is inhibited. Even when the execution control device 4 writes to other registers 42, 43, 44, the original contents are stored in each save register 62 of the save device 6.
, 63° and 64, but the operation is the same as that of the general-purpose register 41, so the explanation will be omitted.

Next, the operation of returning to the checkpoint state and retrying when an abnormal state as described above is detected will be explained. When an abnormal condition is detected, the recovery instruction signal line 56
b is set to 11I and the evacuation and recovery control device 5 is notified. When the recovery instruction signal line 56b reaches %11, the save recovery control device S sends a signal ! through the OR circuit 56. %11 is supplied to is@c, which acts to inhibit the supply of decoded good instructions from the instruction control device 1 in the prohibition (b) path T. When the supply of the subsequent session is stopped, a plurality of arithmetic units (not shown) in the depth control device 4 operate to complete the operation according to the previously supplied command, and all operations are performed. Upon completion, the execution completion signal @45a is set to 111, and the evacuation and recovery control device 5 is notified again. At this point, the ANDIJ path 51 of the evacuation and recovery control device 5 outputs the signal line 57c#r11 because the two inputs, namely the recovery instruction signal M56b and the execution completion signal 11845, are %11.
Let it be I.

When the signal line 57a becomes 111, the gate 5T5 saves the contents of the instruction counter save register 6S of the save device 6 as data@
5sbt to the instruction counter 3s of the instruction control device 3. Also, Gate 571, $72,573,57
4, the general-purpose save register 61 of the save device 6. Base save register 62° Scientific operation save register 63. The contents of status save register 4 are transferred to data lines Slb and 52, respectively.
b, S3b, general-purpose register 41.b of the depth control device 4 via S3b, 54b. Pace register 42. Scientific operation lettuce-43
, is transferred to the status register 44. At this time, the save bit is 111 in each entry of save registers 61 to 64.
Only those entries are transferred to the corresponding entries in registers 41-44.

Further, when the signal line S7c reaches %ll, the contents of the main storage buffer 60 of the save device 6 are transferred to the main memory device 1 via the data line 50b at the gate 5Ts as follows. That is, the address and data stored in the entry of the main memory save buffer 60 indicated by the contents of the save buffer pointer 66 are written to the main memory 1, and the signal 1 [
After setting the save buffer pointer 66 to -l at step 6@d, the entry contents of the main memory save buffer 60 indicated by the contents of the save buffer pointer ε6 are written to the main memory device 1 again. In this way, the entry contents of the main memory save buffer 60 are sequentially written into the main memory 1 until the save buffer pointer 66 reaches O. However, when writing the contents of the main memory save buffer 6 to the main memory 1, any corresponding data is simultaneously written to the buffer memory 2. Through the above operations, all the information is saved to the save device 6 and transferred to the instruction control device 41 and the instruction control device 3. When the depth control device 4 is restored to the main storage device 1$P and the buffer storage device 2, the normal instruction execution operation is restarted and the instruction is retried from the checkpoint.

As explained above, in the present invention, a checkpoint is set.When reading data from the main storage device, the $l# data is saved, and when writing to a register, the original content is saved only once, and an abnormality is detected. By configuring the program so that the saved contents are returned to the main memory or register by 1, it is possible to retry the instruction from the checkpoint without relying on buffer storage methods such as the store-in-balance method or the store-through method. There is an effect. Another advantage is that it can be applied to devices that do not have a buffer storage device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the device according to the invention, FIG. 3 is a block diagram showing an embodiment of the device according to the invention, and FIG. 3 is a detailed description of the peripheral circuit of the execution control device shown in FIG. 2. FIG. 1... Main memory device 2e...Buffer storage device-3-...Command control device 4...Execution control device 5...Evacuation recovery control device 6...Evacuation device Tken@prohibition circuit 21...・Directory 22・・Conflict memory unit 31・Fist・Instruction buffer 3S・・Mocking instruction counter 41・・Working general-purpose register 42・・−Ba≧Register 43・・−Scientific operation register 44・・ΦStatus register 50 to 55 ．． S F---AND times M56...
OR circuit 60...Main memory save buffer 61...-General purpose save register RO2φ...Base save register @3...Scientific operation save register @4・轡・Status save register @5...-Instruction counter save register Is ...11''A save buffer pointer 611.621.@31,641-... Save bit ■1
・Fist/General-purpose write data register ■2...General-purpose read data register I3...General-purpose write address register 94・Φ・General-purpose read address register 501.511, 521, 531, 541, 551゜5
TO~575. Is seam gate 1a, lb, 2m
, 2b, 3a, Ta, 50a ~ 55a, Sob ~ 55
b, 91 m, 12a...fist...data line 40a ~ 45m, 50e ~S7c, 6mb, 66c
. lid, ll5a... meeting/signal line Nla, 93JL, #4a a m a m -
7 To v, z line fang 1 diagram (a) 噸 (b) 4,,,ri -----
OPI OR30PJ 0P4 R+ R2RJ R4

Claims (1)

[Scope of Claims] A memory device for storing instructions and operand data, an instruction control device including an instruction address counter and an instruction decoder and connected to the memory, and a memory device responsive to the instruction control device; In order to read and write operand data in a storage device, an execution control device is connected to the storage device and includes a plurality of registers necessary for executing instructions; a normal state indicating and abnormal state detecting device which is provided in relation to the above, and includes a normal state indicating device which indicates the normal state of the KW number during processing of an instruction, and an abnormal state detecting device which detects a plurality of abnormal states; A transfer path is established between the save storage device, which has a transfer path between the storage device and the instruction address counter, and the save register 7, which has a transfer path between the plurality of registers that overlap the execution control device, and the instruction address counter. a save instruction address counter having a save instruction address counter; and in response to an arbitrary normal state being indicated by the normal state indicating device and execution of the last instruction being decoded at the time of the instruction being completed, the last instruction is a checkpoint device that transfers the contents of the instruction address counter instructing the next instruction to the save instruction address counter; and a checkpoint device that transfers the contents of the instruction address counter to the save instruction address counter; a memory save control device for transferring data to a storage device; and a register save control device that transfers the original contents of this register to the save register when a register included in the execution control device is written after the next instruction. and, in response to any abnormal condition being detected by the abnormality detection device, reversely transfer the contents of the previous i save instruction address counter to the instruction address counter, and transfer the contents of the save register to the previous allocation line. a recovery control device that reversely transfers the contents of the save memory to a register included in the control device and reversely transfers the contents of the save memory to the storage device; Then the operation of the recovery device is completed! Then, in response to an arbitrary normal state being indicated by the normal state indicating device, the execution of the last instruction being decoded at that time is completed, and the operation of the checkpoint device is completed. and a prohibition device that prohibits the operation of the instruction control device until the operation is completed.