JPS58114115A - Device selecting system - Google Patents

Abstract

PURPOSE:To reduce the number of interfaces to simplify the constitution of a selecting system, by transmitting a selecting signal for selecting a lower-level device and a return signal of recognition in time division on bidirectional lines. CONSTITUTION:Second signal lines 101 and 102 connected to a selecting circuit 110 are connected to adapters 110 and 120 respectively, and the first signal line 103 and a turn-back signal line 104 are connected to adapters 110 and 120. Printer controllers 111 and 122, magnetic disc controllers 112 and 123, card reader controllers 113 and 121, and magnetic tape controllers 114 and 124 are connected as lower-level devices to adapters 110 and 120 respectively. The selecting circuit 100 is provided with a register 1, a decoder 2 connected to signal lines 101 and 102, and a transmission register 3 and a gate 9 connected to signal lines 103 and 104. The signal line 103 for selection of lower-level devices and the signal line 104 for return of recognition signals are used in time division as bidirectional lines, thus reducing the number of interface lines.

Description

[Detailed description of the invention] The present invention relates to a device selection scheme.

Particularly, by receiving a rounded first selection signal that selects a lower-order device that is the final selection target and a second selection signal that selects a higher-order device that each commonly controls an arbitrary number of the lower-order devices, one of the lower-order devices is selected. At the same time, the higher-level device involved in pattern selection sends a recognition signal of either itself or the selected lower-level device to the originator (selecting device) of the first and second selection signals. Relates to device selection method.

The recognition signal includes a return signal that simply returns the received second selection signal at the higher-level device, and characteristic information that allows the type and number of the higher-level device involved in the selection or the selected lower-level device to be known. There is. This recognition information is sent back to the selection device and analyzed by microinstructions, etc., thereby making it possible to confirm whether or not the selection has been made correctly.

This type of conventional device selection method uses a unidirectional first signal line for transmitting a first selection signal, a second selection signal line for transmitting a second selection signal to each higher-level device, and a recognition signal. a unidirectional third signal line for replying, a transmission register for holding the first selection signal in the selection device f, and a transmission register for each of the upper device receiving the first selection signal via the first signal at. The receiving buffer includes a receiving buffer, and an M recognition signal generation circuit for each of the upper-level devices, which generates the recognition signal based on the received No. 2 selection signal and the first selection signal outputted from the reception buffer.

In such a conventional configuration, since the first selection signal and the recognition signal are transmitted and received via separate unidirectional signal lines, the number of ink7ace lines between the selection device and the host device increases. There is a drawback.

The purpose of this BA is to provide a device selection system with a small number of ink 7 ace lines.

The method of the present invention is to receive a first selection signal for selecting a lower-order device as a final selection target and a second selection signal for selecting a lower-order device, each of which is a higher-order device that commonly controls an arbitrary number of said lower-order devices. , selects one of the lower-level devices, and the higher-level device involved in the selection also transmits the recognition signal of one of the selected lower-level devices to the first and second lower-level devices.
In a device selection method that sends a reply to a transmission source of a selection signal, a bidirectional M11 signal line for receiving the first selection signal and replying the recognition signal in a time-sharing manner; a transmission register that holds one selection signal received per unit and enters a high impedance state after transmitting the first selection signal via the first signal k; and the first selection signal received via the first signal line k. Recognition for each upper-level device that generates the recognition signal based on a reception register of each upper-level device that holds a selection signal, and the received second selection signal and the first selection signal held by the reception register. a signal generation circuit; a timing generation circuit that generates timing for realizing the time division; and a timing generation circuit that maintains a high impedance state when the reception register receives the first selection signal and that the signal generation circuit A three-value state gate is provided for each of the host devices, which holds the acknowledgment signal when it is generated and sends the reply in response to the timing generated by the timing generation circuit.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In this embodiment, the fourth signal 6103 and two sets of first signal lines 10
1, 102, return signal line 104, and transmission register 3
, a reception register 4, a delay circuit 5 which is a timing generation circuit, a ROM 6 which constitutes a recognition signal generation circuit, a three-value state gate 7, a register 1, and two decoders 2.
8 and a gate 9.

FIG. 2 shows an example of application of the embodiment shown in FIG. 1, and FIG. 3 shows timing for explaining the operation of the embodiment.

In FIG. 2, a printer control device 111, a magnetic disk control device flll12, a card league control device 113, and a magnetic tape control device 114, which are lower devices, are a printer IIIB and a magnetic disk device 112B, respectively.
, card reader 113B and magnetic tape device 11
Adapter 1, which is a host device, performs unique control on 4B.
10 performs common control for these four lower-level devices.

Adapter 120 , T-card reader control device 121 , printer control device 122 , magnetic disk control device 123 , focusing tape control device 124 , and card reading device 121
The same holds true for the relationships between B, printer 122B, magnetic die spread device 123B, and magnetic tape device 124B.

The selection device 100 includes a register 1 and a decoder 2 shown in FIG.
, a transmit register 3 and a gate 9.

Each one of the four lower-level devices, each of which is commonly controlled by the adapters 110 and 120, receives the first selection signal 3' from the selection device 100 via the first signal line 103, and commonly selects ( Half selection) and adapter 110 again! The adapter 120 receives a second selection signal 101' or 1 from the selection device 100 via the second signal line 101 or 102, respectively.
02' (not shown), one of the two half-selected lower-level devices is finally selected. now,
Although the description will proceed assuming that adapter 110 is selected, similar operations are performed when adapter 120 is selected.

The received ninth second selection signal 101' excites the reception register 4 to hold the already received first selection signal 3', and is transmitted to the selection device 1 via the return signal line 104.
The signal is returned as a return signal 104' to the transmission register 3 of 00, and the transmission register 3 is placed in a high impedance state 11K in preparation for receiving the sI signal.

The reception register output 4' is supplied to the decoder 8 and decoded, and the decoder 8 selects one of the printer IIIB, the magnetic disk device 112B, the card reader 113B, and the magnetic tape device 114B, and outputs the selection signal 11.
The three-state gate 7 is made to read out the recognition signal including the type and number of the adapter 1100, which has been written in advance in 111A, 112A, 113A, and 0M6.

On the other hand, the received second selection signal 101' is also input to the delay circuit 5, generates a ting 5', and is supplied to the ternary state gate 7. Three-value state gate 7 is at timing 5'
In response to this, the high impedance state changes from the previous high impedance state to the low impedance state, and the recognition signal 7' read out from the ROM 6 is sent back to the selection device 100 via the jil signal 1i1103.

As a result of the above, the waveform 103' on the first signal line becomes a time-division representation of the first selection signal 3' and the g-identification signal 7', as shown in FIG. 3. In the selection device 100, The recognition signal 7' returned from the gate 9 is analyzed in a core circuit (not shown) by the i microcommand to check whether the adapter terminal 110 has been definitely selected i:! 1. FIG. 4 shows another example of application of the embodiment shown in FIG.

This application example has four input/output processors 100F.

200P, 300P and 400P and 3 subgross + y? 500 P + 600 P k and 70
0P, a memory reader 2000, and a system control unit (system control unit) 1000 are connected to each other via a bus 3000 in an information processing apparatus. Each I/O processor controls any number of adapters. For example, input/output processor 10
0P has 4 Noah tabs/110. '120, 100 and 140 are controlled.

System control unit 1000a controls the entire FI information processing device, including a selection function that treats the input/output processor as a higher-level device and the adapter as a lower-level device.

In this embodiment, only information regarding the adapter, which is a higher-level device, is returned as a recognition signal, but by providing multiple addresses in the ROM 6 and accessing the output of the decoder 8, information regarding lower-level devices can also be sent back. It can be easily included in the recognition signal.

In this embodiment, access to ROM6 is performed by receiving register output 4.
′ is performed only once, but the receive register output 4
By providing a counter that is excited by () and accessing multiple addresses in the ROM several times in succession using the output of this counter, a recognition signal with a large amount of information can be read out. You can also do that.

In this implementation, the recognition signal generation circuit is configured with ROM6, but instead of using ROM, loopback terminals for the number of bits that can identify the adapter are provided for each adapter, and the j12 selection signal is sent to the loopback terminal. By outputting the signal to the ternary state gate 7 via the 3-value state gate 7, the configuration can be greatly simplified.

In this embodiment, all of the recognition signals are returned via the first signal line, but if some of the recognition signals are returned via a separately provided unidirectional return line, the information of the recognition signals can be You can reduce the number of replies when you have a large number of messages and need to reply in multiple parts.

According to the present invention, instead of receiving the first selection signal and replying the M identification signal using a unidirectional signal line, the above-described configuration can be adopted, and instead of receiving the first selection signal and returning the M identification signal using a bidirectional signal line. This allows the number of interface wires to be reduced.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, FIG. 2 shows an application example of the embodiment, FIG. 3 shows the operation timing of the embodiment, and FIG. 4 shows another application example of the embodiment. In, 1 'OO... selection device, 110
,120゜130.140...adapter, 11
1.122...Printer control device, 112,1
23...Magnetic disk control device, 113, 12
1... Card reader control device, 114°124
...Magnetic tape control device, IIIB, 122B
...Printer, 112,123...Magnetic disk device, 113.121...Card reader, 1r4,124...Magnetic chip device,
101, 102...Second signal thin, φ103...
...First signal line, 104...Return signal 8
104.111A, 112 people, 113A, 114A...
...Selection signal -1l ...Register, 2, 8
...Decoder, 3 ...Transmission register, 4 ...Reception register, 5 ...Delay circuit, 6 ...ROM, 7. ...Three-level state gate, 9...Gate, 1'...Register output, 3'...First selection signal, 4'...
...Receive register output, 5'...timing, 7'...U! ! l signal, 101te...
・Second selection signal, weight, 2000... memory, 30
00... Bus, 5oop. 600P, 700P... Sapupu 4 sessa. Agent Patent Attorney Uchihara 3' Figure 3 8d

Claims (3)

[Claims] (1) Receiving a first selection signal for selecting a lower-level device that is the final selection target and a second selection signal for selecting a higher-level device that each commonly controls an arbitrary number of the lower-level devices; A device selection method in which one of the first and second selection signals is selected and the higher-level device involved in the wrinkle selection returns a recognition signal of either itself or the selected lower-level device to the source of the second selection signal. a bidirectional first signal line for receiving the first selection signal and replying the recognition signal in a time-sharing manner; and a second bidirectional signal line for receiving the second selection signal for each of the higher-level devices. a selection signal line, and a transmission register that holds a 1♂ selection signal at the first and second selection signal transmission sources and enters a high impedance state after transmitting the first selection signal via the first signal line; , a reception register for each of the higher-level devices that holds the first selection signal received via the first signal line; and the received second selection signal and the first selection number held by the reception register. a recognition signal generation circuit for each of the higher-level devices that generates the recognition signal based on the recognition signal, a timing generation circuit that generates timing for realizing the time division, and a high impedance register when the reception register receives the first selection signal. state and when the recognition signal generation circuit generates the recognition signal, it is held and the timing '
A device selection system characterized in that a three-value state gate for each of the higher-level devices is provided for making the reply in response to the timing generated by the generation circuit. (2) The device selection system according to claim (1), wherein the lower device is a control device for either an input device, an output device, or an input/output device. (3) The device selection method according to claim (1), wherein the lower device is a control device that commonly controls a control device for either an input device, an output device, or an input/output device.