JPS58112350A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS58112350A
JPS58112350A JP20955081A JP20955081A JPS58112350A JP S58112350 A JPS58112350 A JP S58112350A JP 20955081 A JP20955081 A JP 20955081A JP 20955081 A JP20955081 A JP 20955081A JP S58112350 A JPS58112350 A JP S58112350A
Authority
JP
Japan
Prior art keywords
layer
film
sio
pattern
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20955081A
Other languages
Japanese (ja)
Other versions
JPS622460B2 (en
Inventor
Yorihiro Uchiyama
内山 順博
Takashi Yabu
藪 敬司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20955081A priority Critical patent/JPS58112350A/en
Publication of JPS58112350A publication Critical patent/JPS58112350A/en
Publication of JPS622460B2 publication Critical patent/JPS622460B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To allow a good patterning even with large film thickness and thus attain a desired alpha ray blocking effect, by using an SiO as the alpha ray blocking film material, and accordingly forming the alpha ray blocking film by SiO by a lift- off method. CONSTITUTION:A layer 7 is removed, and, with a layer 6 as a mask, a layer 5 is patterned. Thereafter, an SiO evaporation is performed. It is necessary that the SiO source does not contain the alpha ray source, but a normal SiO evaporation source is satisfactory, then an SiO evaporated layer 8 becomes dull at the end part slightly, but generally a flat film is formed. By removing the layer 5 after the SiO evaporation is finished, the layers 6 and 8 stacked on the layer 5 are removed together, and thus the desired pattern of the SiO layer 8 is obtained. Since the layers 5 and 6 becomes difficult to be removed, when the SiO evaporated layer 8 is evaporated much higher than the layer 6, the thickness of the SiO layer is adjusted by the thickness of the layer 5. When the layer 5 is of resin such as polyimide, the layer 5 is removed by fusing by the mixed solution of e.g. hydrogen and ethylene diamine, etc.

Description

【発明の詳細な説明】 (1)発明の技術公費 本発明は半導体装置特に、α線を有効に阻止した半導体
装置及びその製造方法に係る。
DETAILED DESCRIPTION OF THE INVENTION (1) Technology of the Invention Publicly Funded The present invention relates to a semiconductor device, particularly a semiconductor device that effectively blocks alpha rays, and a method for manufacturing the same.

(2)技術の背景 数年前、α線がICメモリーの情報を撹乱するソフトエ
ラーの原因をなしていることが見い出された。α線源は
パッケージ等に含まれている放射性物質(例えばウラン
、トリウム等)であるが、こうしたものから飛来するα
線を阻止する方法としてポリイiド、シリコーン樹脂等
でコーティングすることが利用されている。しかし、ボ
リイミドを非常に厚くコーティングすることは困離であ
〕、またシリコーン樹脂では耐熱性の点で問題がある等
から、有効なαm[圧平&0HIAが望まれる。
(2) Background of the technology Several years ago, it was discovered that alpha rays cause soft errors that disrupt information in IC memory. Alpha radiation sources are radioactive substances (e.g. uranium, thorium, etc.) contained in packages, etc.
Coating with polyimide, silicone resin, etc. is used as a method for blocking wires. However, it is difficult to coat polyimide very thickly, and silicone resins have problems in terms of heat resistance, so effective αm [applanation & OHIA] is desired.

(3)  従来技術と間一点 α線からのメ篭り一情報等の保護とじては侵入したα線
の情報部への作用を阻止する方味j!論的には考えられ
るが、半導体装置の素子部位へα線が侵入することを阻
止する方法に依ることが実際的である。半導体装置に形
成するα線阻止膜の一般的条件としては■それ自体がα
線を放出しない材料であるとと、■α線を有効に阻止す
るに十分な厚さを得ることが可能であゐこと、0■と関
連して蒸着速度等生産性が高いこと、■バターニングが
容易であるとと、■装置製造条件との関係から耐熱性で
あるとと、などを挙げることができる。
(3) In contrast to the conventional technology, in order to protect information, etc. from alpha rays, there is a way to prevent the intruding alpha rays from acting on the information section! Although theoretically conceivable, it is practical to rely on a method of preventing alpha rays from entering the element portion of the semiconductor device. The general conditions for an α-ray blocking film formed on a semiconductor device are:
It is a material that does not emit radiation, ■ It is possible to obtain a thickness sufficient to effectively block α radiation, ■ It has high productivity such as evaporation rate in relation to 0, ■ Butter (1) heat resistance due to the relationship with device manufacturing conditions;

ポリイミドは主としてそO耐熱性の観点からα線阻止膜
として広く利用されているが、所望の形状及び厚さの膜
を形成する上で問題がある。シリコーン樹脂は耐熱性の
点で問題がある。さらに、例えば8亀ρ、はα線阻止膜
として使用されていないが、それはその蒸着速度が非常
に遅いので生産性が悪いからである。
Polyimide is widely used as an α-ray blocking film mainly because of its heat resistance, but there are problems in forming a film with a desired shape and thickness. Silicone resins have problems in terms of heat resistance. Further, for example, 8-μm ρ is not used as an α-ray blocking film because its deposition rate is very slow, resulting in poor productivity.

(4)発明O目的 以上のような従来技術に於けるaii点に鐙み、優れた
αmft!阻止膜材料を提供すること、及びそうした半
導体装置の有利な製造方法を提供することを、本発明社
目的とする。
(4) Excellent αmft that addresses the aii points in the prior art, which exceed the purpose of the invention! It is an object of the present invention to provide a blocking film material and an advantageous method of manufacturing such a semiconductor device.

(5)発明の構成 本発明の要旨は、5io(si目coo−utonoe
x id@Jをα線阻止膜材料として使用すること、及
びその810によゐα線阻止膜をす7ト・オフ法(L目
を−off  process )で形成することKあ
る。
(5) Structure of the Invention The gist of the present invention is as follows:
It is possible to use x id@J as the α-ray blocking film material, and to form the α-ray blocking film according to 810 by a seven-off process (Lth -off process).

sto蒸着膜社、密度が約2.2f/m”でありてボリ
イ(ドの約1.1〜1.5 fees”よシ大きいので
、α線阻止機能上、同じ膜厚とすればポリイミドより優
れ、換言すれげ所定のα線阻止能率を得る九めに必要た
膜厚はポリイミドよシ薄くても足りるという利点がある
。しかも、耐熱性も優れてお夛(ポリイミドの約400
〜500℃に対して約1100℃まで耐える)、比較的
均一な厚さの膜を形成でき(ポリイミドでは粘度が低い
Oで=−ティングの際円孤状になる)、蒸着速度も高く
(例えば8tO,Klksrn1時に対しIlOは数p
m1分)、さらに後述するリフト・オフ法に依ればパタ
ーニングも可能である。これらOことから一%0はα線
阻止膜材料として優れていることが明らかであろうつ1
9でα′l11m!止勇を廖威すゐ場合、迩常は数十声
〜数百声の展厚属すゐことKなろう。810層O形成方
法は41Kll定はないが、本発IjjOもう一つの側
面である下記のリフト・オフ法に依ゐことができる。
Sto Vapor Film Co., Ltd. has a density of approximately 2.2 f/m", which is larger than polyimide (approximately 1.1 to 1.5 feet"), so in terms of α-ray blocking function, it is better than polyimide if the film thickness is the same. In other words, it has the advantage that the film thickness required to obtain a specified α-ray blocking efficiency is even thinner than that of polyimide.Furthermore, it has excellent heat resistance and is thicker (approximately 400 times thinner than polyimide).
It can withstand up to about 1100℃ compared to ~500℃), can form a film with a relatively uniform thickness (polyimide has a low viscosity and becomes arcuate when tinged with O), and has a high deposition rate (e.g. 8tO, IlO is several p for Klksrn1 hour
m1 minutes), and patterning is also possible using the lift-off method described later. From these O, it is clear that 1%0 is excellent as an α-ray blocking film material.1
α′l11m at 9! If you are trying to make a stop, you will probably have dozens to hundreds of voices to play. Although there is no specific method for forming the 810 layer O, it can rely on the following lift-off method, which is another aspect of the IjjO of the present invention.

リフト・オフ法とは、最終パターンを形威すべき場所(
便宜上「パターン部位」と称する。)以外の場所に最終
パターンを形成すべき材料と14なる材料ムでパターン
部位よ〉高い位置壜での層を形成し、次いでこの段差O
ある構造O上に最終パターンを形成すべき材料lによる
層を形成又は積層せしめ、そO後材料ムをその上に積層
された材料1と共に除去することによりて材料lをパタ
ーン部位に喪す方法を指称する。本発明では、材料Bが
StOであ)、パターン部位は!l1OIIIa線阻止
膜を形成すべき半導体素子部位(第1図の3参照)であ
る。
The lift-off method is the location where the final pattern should be applied (
For convenience, this will be referred to as a "pattern site." ) A layer is formed at a position higher than the pattern area using the material to form the final pattern and the material 14 at locations other than ), and then this level difference O
A method of forming or laminating a layer of material l to form a final pattern on a certain structure O, and then removing the material l together with the material laminated thereon, thereby removing the material l at the pattern site. point to. In the present invention, material B is StO), and the pattern portion is ! This is the semiconductor element portion (see 3 in FIG. 1) where the l1OIIIa line blocking film is to be formed.

以外、実施例を用いて具体的に説明する。The remainder will be specifically explained using examples.

(6)発aO爽施例 第1図において、ウェーノSl上に半導体素子のチップ
2が形成されている。チップ2のうちα線阻止膜で保護
すべき素子部分3は斜線で示した。
(6) Example of aO Refreshing In FIG. 1, a chip 2 of a semiconductor element is formed on Waeno Sl. The element portion 3 of the chip 2 that should be protected by an α-ray blocking film is indicated by diagonal lines.

第2図を参照しながらリフト・オフ法に依る工程を説明
するが、簡単化するために、第2図中では半導体チップ
2は省略した。
The process based on the lift-off method will be explained with reference to FIG. 2, but the semiconductor chip 2 is omitted in FIG. 2 for simplicity.

先ず、半導体素子を形t&後のウェーハ1上に非パター
ン部を持ち上げるために層5を形威した。
First, a layer 5 was formed to lift the non-patterned parts onto the wafer 1 after forming the semiconductor device.

層5はポリインド等の耐熱性w、iiであることが好着
しい、形成できる840層の厚さはほぼとの層5の厚さ
であゐので、この層5の厚さを840層の所望の厚さ程
度、約10〜数100μに形威し喪。
It is preferable that the layer 5 is made of heat resistant material such as polyind.The thickness of the 840 layers that can be formed is approximately the same as that of the layer 5. Shape it to the desired thickness, about 10 to several 100 microns.

この層5を直接パターニングすることよシ威りてもよい
が、この上K例えば、低温CVD、スパッタリング勢に
よ〉、例えばP8GII、 g轟、N4層、810、層
勢を形威しえ、この層6社sio蒸着の際にll根(傘
)の役割をする部分であ)、パターン部の層5を除去す
る処mkよりて除★されず、かつ8i0堆積層を支持可
能な強度を有しているぺ自である。
Although it is possible to pattern this layer 5 directly, it is also possible to pattern the layer 5 by, for example, low-temperature CVD or sputtering, such as P8GII, N4 layer, 810 layer, etc. This layer plays the role of a root (umbrella) during the 6SIO deposition, and is not removed by the process of removing layer 5 in the pattern area, and has the strength to support the 8I0 deposited layer. It is my own privilege to have it.

層6も直接パターニングすることよp威りてもよいが、
さらにとO上に慣用のレジスト7を塗布し、レジストパ
ターン形威し先後、エツチング等によってパターン化し
え。これらの処理は慣用の手法に依り九。
Although layer 6 may also be patterned directly,
Furthermore, a conventional resist 7 is applied on top of the resist 7, and after the resist pattern is formed, a pattern is formed by etching or the like. These treatments depend on conventional methods.

次いで、層7を#資すると共に層6をマスクとして層6
をパターニングした。これらの処理は同一工程であるこ
とが好ましく、例えば一般りIl脂であれば0.プラズ
マ中で処理することなどに依ることができた。このとき
の様子は第2図−)に示されているが、Wiに見られる
ように層5の灰化又はエツチングは層6を廂として軒0
下壕で進行した。この廂の形成asto層蒸着後に層5
及び6を除去するのを容易にする効果がある。
Next, layer 6 is applied with layer 7 and layer 6 is used as a mask.
patterned. It is preferable that these treatments are carried out in the same process.For example, in the case of general lubricant, 0. It was possible to rely on treatments such as processing in plasma. The situation at this time is shown in Figure 2-), but as seen in Wi, the ashing or etching of layer 5 is similar to that of layer 6.
It proceeded in the lower bunker. After the formation of this ASTO layer, layer 5
and 6 have the effect of making it easier to remove them.

この後、、Btoの蒸着を行なった。8飯0源はα−源
を含有しないものである必要があるが、通常のS&O蒸
着源であれば十分である。jlZ図(C)に見られるよ
うに、s&0蒸着層8は端部がややダレるが、一般的に
平坦な膜が形成された。8io蒸着終了後層5を除去す
ることによりて、層5の上に積層している層6及び8を
一緒に除去し、8五〇層8の所望なパターンを得た(第
2図(d)参照) 、 1840s着層8を層6よシあ
tbに高くなる壇で蒸着すると層5及び6の除去が困難
になるので、前述のように層5の厚さで810層の厚さ
を調節した0層5がポリペ(ド等O樹脂の場合には、層
5は例えばヒドラジンとエチレンジアミンとの混合液な
どで溶解することによって除去した。
After this, Bto was deposited. Although it is necessary that the source does not contain an α-source, a normal S&O deposition source is sufficient. As seen in Figure (C), the s&0 vapor deposited layer 8 was slightly sagging at the edges, but a generally flat film was formed. By removing layer 5 after the 8io vapor deposition, layers 6 and 8 laminated on layer 5 were removed together to obtain the desired pattern of 850 layers 8 (see Figure 2(d)). ), if the 1840s deposited layer 8 is deposited on a platform that is higher than layer 6, it will be difficult to remove layers 5 and 6, so as mentioned above, the thickness of layer 5 will be 810 layers. When the adjusted O layer 5 was an O resin such as Polype, the layer 5 was removed by dissolving it with, for example, a mixed solution of hydrazine and ethylenediamine.

以上、リフト・オフ法によるS:Oa影形成実施例を用
いて説明したが、これらの41走は本発明を限定するも
のではない。
Although the explanation has been given above using an example of S:Oa shadow formation using the lift-off method, the present invention is not limited to these 41 runs.

α線阻止展として8i011を利用する場合、一般的に
膜厚が相当に大きくなるので、sio膜のパターニング
に際して、エツチングは困難であplま九いわゆるメタ
ルマスク法ではマスクとウェーハとの間隙に810が廻
シ込むという間mがあるのに対して、本発明に係るリフ
ト・オフ法では膜厚が大きくて4良好カバターニングが
可能になるという利点がある。
When using 8i011 as an α-ray blocking agent, the film thickness is generally quite large, so etching is difficult when patterning the SIO film.In the so-called metal mask method, the 810 In contrast, the lift-off method according to the present invention has the advantage that the film thickness is large and good coverage can be achieved.

(7)発明の効果 以上の説明oM’) 、本発明に依って提供される半導
体装置及びその製造方法に於いて、所望なα線阻止効果
が達成でき、4IVCその工業的利用性は大である。
(7) Effects of the Invention oM') In the semiconductor device and the manufacturing method thereof provided by the present invention, the desired α-ray blocking effect can be achieved, and the industrial applicability of 4IVC is great. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はウェーハ上に彫成し丸帯導体素子における84
011パターンを示す図及びそのパターンを形成するリ
フト・オフ法の一工程における前記図の部分拡大断面図
である。第2vAは本発1111に依シ8i0111を
リフト・オフ法で形成する工程を順次示す概略断面図で
ある。 l・・・ウェーハ 2・−半導体素子、 3・・・α線素子膜(8i0)パターン、4・・・端子
咎、 5・・・耐熱性樹脂層、 6・・・膜、 フ・・・レジスト、 8・・・S偽0蒸着膜。 特許出馳人 富士通株式査社 特許出願代理人 弁理士青水 朗 弁理士西舘和之 弁理士内田幸男 弁理士 山 口 昭 之
Figure 1 shows 84 mm in a round conductor element carved on a wafer.
FIG. 2 is a diagram showing a 011 pattern and a partially enlarged cross-sectional view of the diagram in one step of a lift-off method for forming the pattern. 2nd vA is a schematic cross-sectional view sequentially showing the steps of forming a base 8i0111 on the present invention 1111 by a lift-off method. l...Wafer 2--semiconductor element, 3...α-ray element film (8i0) pattern, 4...terminal layer, 5...heat-resistant resin layer, 6...film, film... Resist, 8...S false 0 vapor deposited film. Patent originator Fujitsu Ltd. Patent application agent Akira Aomi Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akira Yamaguchi

Claims (1)

【特許請求の範囲】 1、 α線阻止膜がgtolに成る仁とを4I黴とすゐ
半導体装置。 2、  ll1Oよ形成るα線阻止膜を有する半導体装
置の製造方法Klいて、gio展で被覆されるべき半導
体素子部を含む基板上に下層を形威し、皺下層を選択的
にエツチングし、そO上の全mVcst。 膜を形成し丸後、前記下層を除去するととによりてその
上部に積層されてい九810膜をも111*L、よって
所腿なパターンを有すゐ8i0展を形成するととを特徴
とする、半導体装置の製造方法。 3、 8NO膜で被覆されるべ1半導体素子部を含む基
板上に最終s10膜として所望な厚さ程度のポリイミド
層を形成し、その上にポリイミド層のエツチング処理及
びStO膜形成処理に耐える薄い鳳板層を形成し、諌屋
根層を必要に応じてレジスト手法を用いて選択的にエツ
チングし、それKよりて形成されたパターンを利用して
前記ボリイずド層をそれと同じパターンにエツチングし
、それから全面に前記所望な厚さのSIO膜を形成し、
その後前記ポリイミド層を除去することによってその上
に被着していたSiO膜をも除去し、よって所望な厚さ
及びパターンを有するS稙腰を形成することをIFI徴
とする、特許請求の範[82項記載の方法。
[Claims] 1. A semiconductor device in which the α-ray blocking film is made of Gtol and 4I mold. 2. A method for manufacturing a semiconductor device having an α-ray blocking film formed by ll1O, forming a lower layer on a substrate including a semiconductor element portion to be covered by gio-etching, selectively etching the wrinkled lower layer, The total mVcst on soO. After forming the film and removing the lower layer, the 9810 film laminated on top of the film is also formed into a 111*L pattern, thus forming an 8i0 pattern with a thick pattern. A method for manufacturing a semiconductor device. 3. A polyimide layer of desired thickness is formed as the final S10 film on the substrate containing the semiconductor element portion to be covered with the 8NO film, and a thin polyimide layer that can withstand the etching process of the polyimide layer and the StO film formation process is formed on top of it. Form a tungsten plate layer, selectively etch the ridged roof layer using a resist method as needed, and use the pattern formed by this method to etch the borded layer into the same pattern. , then forming an SIO film of the desired thickness on the entire surface,
The claim is that the IFI feature is that by subsequently removing the polyimide layer, the SiO film deposited thereon is also removed, thereby forming an S-shaped film having a desired thickness and pattern. [The method described in item 82.
JP20955081A 1981-12-26 1981-12-26 Semiconductor device and manufacture thereof Granted JPS58112350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20955081A JPS58112350A (en) 1981-12-26 1981-12-26 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20955081A JPS58112350A (en) 1981-12-26 1981-12-26 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS58112350A true JPS58112350A (en) 1983-07-04
JPS622460B2 JPS622460B2 (en) 1987-01-20

Family

ID=16574666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20955081A Granted JPS58112350A (en) 1981-12-26 1981-12-26 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS58112350A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5476066A (en) * 1977-11-30 1979-06-18 Toshiba Corp Pattern forming method
JPS55128845A (en) * 1979-03-28 1980-10-06 Hitachi Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5476066A (en) * 1977-11-30 1979-06-18 Toshiba Corp Pattern forming method
JPS55128845A (en) * 1979-03-28 1980-10-06 Hitachi Ltd Semiconductor device

Also Published As

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JPS622460B2 (en) 1987-01-20

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