JPS58110037A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58110037A JPS58110037A JP56208077A JP20807781A JPS58110037A JP S58110037 A JPS58110037 A JP S58110037A JP 56208077 A JP56208077 A JP 56208077A JP 20807781 A JP20807781 A JP 20807781A JP S58110037 A JPS58110037 A JP S58110037A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- contact
- substrate
- type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims 2
- 229910020489 SiO3 Inorganic materials 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 2
- 229910019142 PO4 Inorganic materials 0.000 abstract 1
- 230000007423 decrease Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 abstract 1
- 239000010452 phosphate Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、ＬＳＩ等の微細構造素子におけるコンタクト
不良率が低い半導体装置の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device with a low contact failure rate in a microstructure element such as an LSI.
最小寸法が２〜：３＃Ｉ程度のＬＳＩ素子の製造におい
ては、素子寸法に余裕度がなく、この程度の小さな寸法
にもなると、例えばＭＯＳ −ＦＥＴではシミ領域でも
ある。そして、この程度の寸法の素子で′はそのコンタ
クト穴も２〜３μｍで、しかもマスク合せの余裕度等の
制約からコンタクト穴の半分程度はＬＯＣＯ８の厚い酸
化峡で覆われてしまっており、実質的なコンタクト穴の
サイズはｌμｒｒＬ２程度となる。したがって、この実
質的なコンタクト穴のサイズを工、チング量の大きさで
制御するご七が困難となり、半導体素子のコンタクト不
良率が大きくなるという問題があった。In the manufacture of LSI elements with a minimum dimension of about 2 to 3 #I, there is no margin for element dimensions, and such a small dimension is also a stain area in, for example, a MOS-FET. In an element of this size, the contact hole is also 2 to 3 μm, and due to constraints such as mask alignment margin, about half of the contact hole is covered with a thick oxidation layer of LOCO8. The typical size of the contact hole is approximately lμrrL2. Therefore, it becomes difficult to control the actual size of the contact hole by the amount of machining and chipping, and there is a problem in that the contact failure rate of semiconductor devices increases.
本発明の目的は、このような問題を解決するため、ＬＳ
Ｉ等の微細構造素子における微細寸法コ／タクトのコン
タクト面積を三次元的に拡大するこ、！−に！５、：７
ンタクト不良率が低いセルファラインコンタクト穴形成
ノロセスを含む半導体装置の製造方法を提供することで
ある。The purpose of the present invention is to solve such problems by
To three-dimensionally expand the contact area of fine dimensions and tact in fine structure elements such as I! -to! 5, :7
It is an object of the present invention to provide a method for manufacturing a semiconductor device including a self-line contact hole formation process with a low contact defect rate.
次に、本発明に係る半導体装置の製造方法を実施例に基
づいて説明する。第１図は、開穴部形成用レジスト・ぐ
ターンの断面図であって、Ｐ型（もしくはＮ型）のシリ
コン基板１上にＬＯＣＯ８酸化膜２とＮ型（もしく・は
Ｐ型）拡散層３を形成し、さらにこの上部にＳ ｉＯ３
絶縁酸化膜４が形成されている。なお、５はポリシリコ
ン層で、例えばダート電極に相当するものである。この
ような構造を有する基板の上部にホトレノストを塗布し
てホトレジストノ母ター７６を設け、ホトエツチングに
よシセルファラインコンタクト穴用開穴部７をノぐター
ン形成する。Next, a method for manufacturing a semiconductor device according to the present invention will be described based on examples. FIG. 1 is a cross-sectional view of a resist pattern for forming an opening, in which a LOCO8 oxide film 2 and an N-type (or P-type) are diffused on a P-type (or N-type) silicon substrate 1. Layer 3 is formed, and SiO3 is further formed on top of this layer 3.
An insulating oxide film 4 is formed. Note that 5 is a polysilicon layer, which corresponds to, for example, a dirt electrode. A photoresist matrix 76 is provided by applying photorenost to the upper part of the substrate having such a structure, and a hole 7 for a self-aligned contact hole is formed by photoetching.
このようにして形成されたホトレジストノやター７６を
エツチングマスクとしてＳ ｉＯｓ絶縁酸化膜４をエツ
チングする。このときのエツチング量はＳ ｉＯｓ絶縁
酸化ＪＩ４の膜厚だけではなく、コンタクト面積を三次
元的に拡大するために更にエツチングし、オーバエツチ
ングとするのが望ましい。しかし、ホトレジストノＪ？
ターン６の横方向へのエツチング入ｐ込み量は最小限に
抑える必要があるため、エツチングに指向性を持つプラ
ズマエツチング法を用いることが望ましい。例えばＳｉ
Ｏ絶縁酸化膜４の膜厚が２０００＾である場合には、作
用ガスとして０４Ｆ、 ｆ！ス（１００％）を用い、そ
の全ＥＥ Ｏ，０７Ｔｏｒｒとし、高周波電力２００Ｗ
の状態で約３分間エツチングし、さらに２分間程度のオ
ーバエツチングを行なうと、５ｉｎ３絶縁酸化膜４下の
拡散層３の表面が１００Ｘ程度工、チングされる。The SiOs insulating oxide film 4 is etched using the photoresist layer 76 thus formed as an etching mask. The amount of etching at this time is not limited to the thickness of the SiOs insulating oxide JI4, but is preferably further etched and over-etched in order to three-dimensionally expand the contact area. However, Photoresist No.J?
Since it is necessary to minimize the amount of etching intrusion into the turns 6 in the lateral direction, it is desirable to use a plasma etching method with directional etching. For example, Si
When the thickness of the O insulating oxide film 4 is 2000^, the working gas is 04F, f! (100%), its total EE O, 07 Torr, high frequency power 200W
When etching is carried out for about 3 minutes in this state and over-etching is further carried out for about 2 minutes, the surface of the diffusion layer 3 under the 5in3 insulating oxide film 4 is etched by about 100X.
こ−一のようなエツチング工程によシ、第２図に示され
声開穴部８が形成される。Through this etching process, the opening 8 shown in FIG. 2 is formed.
次に、例えばこの開穴部８を形成する際に用いたホトレ
ジストノやターン６をマスクとしてＮ型拡散層（もしく
はＰ型）３と同一の伝導型の不純物、例えばリンをイオ
ン注入法等で打ち込み、第３図に示されたイオン注入領
域９を形成する。なお、イオン注入領域９はガス拡散法
やドーグオキサイド法によって形成してもよい。Next, an impurity of the same conductivity type as the N-type diffusion layer (or P-type) 3, such as phosphorus, is added by ion implantation using the photoresist layer or turn 6 used to form the hole 8 as a mask. Implantation forms the ion implantation region 9 shown in FIG. Note that the ion implantation region 9 may be formed by a gas diffusion method or a dogu oxide method.
このようにして形成された開穴部８にし・シスト・ぐタ
ーン除去した後、第４図に示されたように電極１０を形
成することにより、セルファラインコンタクトが形成さ
れる。このとき、上述のイオン注入によシ、Ｓｔ基板ｌ
に拡散層３と同伝導型の不純物のイオン注入領域９が形
成されているので、三次元的なコンタクト形成を持つ電
極１０を設けてもＳｔ基板ｌとＮ型拡散層３とが短絡状
態となることはない。After removing cysts and gas from the hole 8 thus formed, an electrode 10 is formed as shown in FIG. 4, thereby forming a self-line contact. At this time, due to the above-mentioned ion implantation, the St substrate l
Since an ion-implanted region 9 of an impurity of the same conductivity type as the diffusion layer 3 is formed in the ion implantation region 9, the St substrate 1 and the N-type diffusion layer 3 will not be short-circuited even if the electrode 10 with three-dimensional contact formation is provided. It won't happen.
以上説明したように本発明においては、拡散層と同一伝
導型の不純物をコンタクト形成用の開穴部を介して基板
に注入するので、コンタクト形成用の開穴部をオーバエ
ツチングしてコンタクト面積を三次元的に拡大できるた
め、コンタクト不良率を極めて低く抑えることが可能と
なる。As explained above, in the present invention, an impurity of the same conductivity type as that of the diffusion layer is injected into the substrate through the contact forming hole, so the contact area is increased by over-etching the contact forming hole. Since it can be expanded three-dimensionally, it is possible to keep the contact failure rate extremely low.
第１図は開穴部形成用レノスト・フタ−／を示す断面図
、第２図は開穴部形成後のパターンの断面図、第３図は
不純物注入後の断面図、第４図は開穴部に電極を設けた
場合の断面図である。
１・・・Ｓｉ基板、２・・・ＬＯＣＯ８酸化膜、３・・
・拡散層゛、４・・・Ｓｉ絶縁酸化膜、６・・・コンタ
クト穴形成用レノストノＪ？ターン、９・・・イオン注
入領域。
第１図
６
第３図
６ ′
第４図Figure 1 is a cross-sectional view showing the Lennost lid for forming the opening, Figure 2 is a cross-sectional view of the pattern after the opening is formed, Figure 3 is a cross-sectional view after impurity implantation, and Figure 4 is the opening. FIG. 3 is a cross-sectional view of a case where an electrode is provided in a hole. 1...Si substrate, 2...LOCO8 oxide film, 3...
・Diffusion layer, 4...Si insulating oxide film, 6...Renostono J for contact hole formation? Turn, 9...Ion implantation region. Fig. 1 6 Fig. 3 6 ' Fig. 4
Claims (3)
半導体基板表面上に、コンタクト用レジスト・ぞターン
を形成した後、該素子分離絶縁層領域をオーバーエツチ
ングしてコンタクト用開穴部を形成する工程、該コンタ
クト用しジストＡ？ターンをマスクとして半導体活性領
域の拡散層と同一伝導型の不純物を半導体基板に注入す
る工程、および該レジストパターン除去後にコンタクト
用開穴部に電極を設ける工程とを有することを特徴とす
る半導体装置の製造方法。(1) After forming a contact resist pattern on the surface of a semiconductor substrate having a semiconductor active region and an element isolation insulating layer region, the element isolation insulating layer region is overetched to form a contact hole. In the process of forming a resist for the contact A? A semiconductor device comprising the steps of: implanting an impurity of the same conductivity type as a diffusion layer in a semiconductor active region into a semiconductor substrate using a turn as a mask; and providing an electrode in a contact opening after removing the resist pattern. manufacturing method.
ト穴であることを特徴とする特許請求の範囲第（１）
頂に記載の半導体装置の製造方法。(2) Claim No. (1) characterized in that the contact hole is a self-line contact hole.
The method for manufacturing the semiconductor device described at the top.
する特許請求の範囲第（１）項に記載の半導体装置の製
造方法。(3) The method for manufacturing a semiconductor device according to claim (1), wherein the impurity is introduced by ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56208077A JPS58110037A (en) | 1981-12-24 | 1981-12-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56208077A JPS58110037A (en) | 1981-12-24 | 1981-12-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58110037A true JPS58110037A (en) | 1983-06-30 |
Family
ID=16550256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56208077A Pending JPS58110037A (en) | 1981-12-24 | 1981-12-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58110037A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07263556A (en) * | 1995-03-24 | 1995-10-13 | Hitachi Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5585041A (en) * | 1978-12-22 | 1980-06-26 | Hitachi Ltd | Semiconductor device and its preparation |
-
1981
- 1981-12-24 JP JP56208077A patent/JPS58110037A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5585041A (en) * | 1978-12-22 | 1980-06-26 | Hitachi Ltd | Semiconductor device and its preparation |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07263556A (en) * | 1995-03-24 | 1995-10-13 | Hitachi Ltd | Semiconductor device |
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