JPS58108829A - Logical integrated circuit - Google Patents

Abstract

PURPOSE:To detect all single short-circuit faults between decoding lines, product term lines, and output lines in a programmable logical array by adding simple checking logic irrelevantly to a normal logical function. CONSTITUTION:In an AND array 2, AND signals of signals of decoding lines where AND devices (corresponding to mark ''.'' at 211) are present are generated on respective product term lines 21-27, and in an OR array 3, OR signals of signals of product term lines where OR devices (corresponding to mark ''X'' at 311) are prevent are generated on respective output lines 31-33. Thus, normal output signals f1-f3 and a checking observation output signal (g) are obtained. In a decoder, if a short-circuit fault functioning as AND occurs between the input line of an external input signal x1 and the output line of an inverter 11, the fault can not be detected by a syndrome test of normal outputs f1-f3, but is detected from variation of said output signal (g).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an easily testable logic integrated circuit, and more particularly to a programmable logic array that is easy to test for signal line short circuit failures.

As logic integrated circuits become larger and more complex due to advances in LSI technology, fault testing is becoming increasingly difficult and expensive. The main inspection costs are test pattern generation cost and test execution cost, but in general, logic LSI/VLSI
To generate test patterns, it is necessary to use a large scale machine for a long time, and to execute the test, a high-grade machine that can apply a large number of test patterns at high speed and judge pass/fail in a short time is required. Since it is necessary to use a tester, the inspection cost becomes very high, which causes problems. For this reason, various methods of configuring logic circuits that are easy to test have been proposed for the purpose of reducing testing costs.

IEEE Trans, Coynput, C-2
9, PP, 442-451゜June 1980+ r
J,5avir,' syndronle-T
eatableDesign of Com4inat
In ional Circuit M'J, for a combinational logic circuit with 1h input, all 2n inputs are input once, and the number of times the output becomes 1 (hereinafter referred to as syndrome) is counted to determine the quality of the circuit. A method of fault testing (hereinafter referred to as a syndrome test) is proposed, and a method of configuring a circuit so that all single-logic stuck-at faults can be detected is shown. However, this easy-to-test configuration of the combinational logic circuit does not guarantee detection of short-circuit failures between signal lines.

Short-circuit faults in signal lines are not necessarily easier to handle than logic stuck-at faults, so they have not been sufficiently studied as a subject for inspection. However, as the density of circuits has increased in recent years, the frequency of short-circuit failures in signal lines has increased, so it is important to consider them as targets for failure inspection.

:'1 In view of this situation, the object of the present invention is to develop a programmable logic array, which is considered to be a useful component for realizing VLSI.
An object of the present invention is to provide a logic integrated circuit in which all single short circuit faults that function as wired R or OR between adjacent signal lines can be detected by the syndrome test described above. According to , each takes a signal pair (-l to X2, X2 Ji) as input, and Mata -t (negation of Xz & -1) and Mata! & (denial of X)
1.2, where the logical sum of Xru~+hXwk, the logical sum of Xm1t and Xy, and the logical sum of Xth=r and・、
tl..., a programmable AND array that generates an arbitrary AND of the output signals of the 2-bit decoder and the decoder group, and a programmable AND array that generates an arbitrary OR of the output signals of the AND array. In a programmable logic array consisting of a logical OR array, each of the first, second, ..., Ryu, ..., and G decoders is used for fault testing regardless of the normal logic realized by the logic play. A logical integrated circuit is obtained in which a logical product of the second and third outputs of the logical product array is generated in the logical product array, and the output signal is used as an observation signal to facilitate failure testing.

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the integration is easily realized by ordinary technology, so a description thereof will be omitted.

FIG. 1 shows a concrete example of the testable logic integrated circuit of the present invention.
FIG. 2 is a circuit diagram showing an example. In the same figure, 11 to 13 are 2
P, T decoder, 2 is a programmable AND play,
3 is a programmable OR array, 116 to 119 are decode lines, 21 to 27 are product term lines, 31 to 33 are output lines, 211 is a device with an AND function, 311 is a device with an OR function, is the external input signal, fl-'
-fl is a normal output signal, and -fl is an observation output signal for failure inspection.

FIG. 2 is a circuit diagram showing a specific example of the decoder 11 shown in FIG.
15 is a NAND gate, in the same figure, NAND
At gates 112 to 115, Xt+X and Yu+X respectively.
The operations s, However, 10 represents the logical sum, Xl, X2, etc. represent the negation of the Xl, Xs logic, and the same applies to the others. The same applies to decoders 12 and 13.

Referring again to FIG. 1, in the logical product array 2, each product term line 2
1 to 27, the logical result of the signals of the decode lines where the device (corresponding to the * mark in 211) exists is X! Xl
X4 Xs Xs, X+ Xll X4 Xs
Xs, Xs Xs Xs, Xr X2
X4, X s X2, X5XsXs and CXtXz +
X1Xz) (XllX4 +X5X4) (XsXa
+X5Xtr) are respectively generated, and in the OR array 3, an OR device (31
The logical sum of the signals of the product term lines that correspond to the x mark of 1 is generated. Therefore, the normal output signal f′1
-fa and the inspection observation output signal G can be expressed by the following equation.

Fang=XtXg+X5Xz) (Yu Doko XBX4)
(Mu + X1 1
7.17.16.8.

Decoder 11 in FIG. 1 configured as shown in FIG. 2
, the input line of the external input signal X1 and the inverter 11
When a short circuit fault occurs between the output lines of 1 and 1, which functions as an AND, the normal outputs P'l and J・1 remain unchanged, but
Di! changes as shown below.

N;=X Spirit X5X4X@X@→-X*X*Xa+XaX
sXa However, F! Since the syndrome of is the same as that of f2, the above-mentioned short-circuit fault cannot be detected by the normal output f-fs syndrome test. On the other hand, the observation output signal for inspection changes as follows.

Qi=XIX! (3?sX4+XsX< ) (Xs
Xa + Xs

In addition, the same can be said about the AND type short circuit failure between the input line of the external input signal X in the decoder 13 and the output line of the inverter (corresponding to 110 of the second gull) that outputs Xs.

As described above, by adding the inspection observation output signal S, it becomes possible to detect short-circuit failures that could not be detected by the syndrome test of the normal outputs F1 to Fm. the result,
In the logic array configured as shown in Figure 1, single short circuit faults between decode lines, product term lines, and output lines, as well as single short circuit faults that do not cause a feedback loop in each decoder, are all normal output signals. and can be detected by a syndrome test of the inspection observation signal.

FIG. 3 is a circuit diagram showing another specific example of the decoder 11 shown in FIG.
15 is an OR gate. Even when the decoder shown in FIG. 3 is used in place of the decoder shown in FIG. 2, the same consideration can be given as above.

The present invention has 6 human power XI =X@, 3 outputs f'1-f-1
The explanation was given using an example in which the product term is 6, but in general α
Of course, this can be applied when the product term is γ with λ power and β output. Furthermore, although the embodiment shown in FIG. 1 is for a logic array using a 2-bit decoding method, in the case of a logic array using a 1-bit decoding method,
Generate the logical product I The same result can be obtained by
As explained in detail above, the logic integrated circuit of the present invention can be considered as follows.
Single short-circuit faults between decode lines, between product term lines, and between output lines in siprogrammable logic arrays by adding simple test logic independent of the normal logic functions implemented in the circuit, and each All single short-circuit faults that do not result in feedback loops in the decoder can be detected by cheap and simple test means;
/VLSI This has a significant effect in reducing inspection costs.

[Brief explanation of the drawing]

1 is a circuit diagram showing a specific example of the logic integrated circuit of the present invention, FIG. 2 is a circuit diagram showing a specific example of the decoder 11 of FIG. 1, and FIG. 3 is a circuit diagram of the decoder 11 of FIG. 1. 12 is a circuit diagram showing another specific example of No. 11. FIG. In the figure, 11 to 13...decoder 116 to 119...decode line 2......logical product array 21 to 27...product term line 211...AND function Device 3 with...
. . . OR arrays 31 to 33 . . . Output lines 311 . . . Devices with OR function 110.11
1...Inverter 112-115...
NAND gate 410, 411...Inverter 412-413...OR gate Xl"Xs...
...External input signal f1~f1...Normal output signal 6...
1, each representing the observation output signal for inspection, Fig. 1 Pigeon 2 Fig. 1 w1jS diagram procedure amendment 1 shot) 58.2. -3 Mr. Commissioner of the Patent Office, Month, Day, 1980, 1, Indication of the case 1982 Patent Application No. 1903
No. 31 No. 3, Relationship with the case of the person making the amendment Applicant: 5-33-1-4, Shiba, Minato-ku, Tokyo, Agent: 5 Detailed description of the invention in the specification subject to amendment 6 Contents of the amendment 1) r'('s ”z+x+
-1's) J is corrected to "ni1me+!, town)・". 2) Page 6, line 6 of the specification K r (xsxa+ xmx
a) (xhJs+ :ll5g*) J is r (X's-Z'a+ Jsxt)" (-1s
Correct as i・+J's&s)J. 3) @Correct rGJ on page 6, line 11 of the specifications to [tJ. 4) Specification page 6 line 15 K rl = ZIZt+
3:r31:*>(424+gB:t4) (31@
-t@+31626) J is corrected as [1=(11t+Jt 31t)・(TeSte4+41x4)・(iBZ@10MB:l:a)”. 5) On page 6, line 17 of the specification, “Output R+ '2 s F
"m and G" is corrected to "output fl-h-fs and l". 6) On page 7, line 6 of the specification, K "crow's syndrome" is corrected to "f-'s syndrome." 7) Correct rGJ to r/J on page 7, line 10 of the specification. 8) On page 7, line 16 of the specification section, ``ll0J in Figure 2 is corrected to ``ll0J in Figure 2.'' 9) On page 7, line 20 of the specification, ``ll0J in Figure 2'' is written as r Fl-'3J. Correct it as r fl-fsJ.

Claims (1)

[Claims] Each takes a signal pair (Xx4-t,X!&) as input, and Xzk-1 (negation of
The logical sum of , the logical sum of Xs button 1 and X field, the logical sum of The logical sum of 1 and 1 is the 1st.
2.3 and the fourth output 1.2,...tl
..., a programmable AND array that generates an arbitrary AND of the output signals of the 2-bit decoder and the decoder group, and a programmable logic that generates an arbitrary OR of the output signals of the wrinkled AND array. In a programmable logic array consisting of a sum array, the above-mentioned 1.2..., t, .・A logic integrated circuit characterized in that a logical product of the second and third outputs of each decoder is generated in a Zengki array, and a wrinkle output signal is used as an observation output signal to facilitate failure inspection. .