JPS58108095A - Memory - Google Patents

Abstract

PURPOSE:To allow a memory cell to have characteristic data in initial power-up operation by connecting the gates of depletion type load MOSFETs of two inverters which form an FF to the sources and drains reciprocally. CONSTITUTION:The gates of enhancement type transistors (TR) QE and QE forming the FF of a memory cell and depletion type load MOSFETs QD1 and QD2 constituting the 1st and the 2nd inverters are connected to the sources and drains reciprocally. Therefore, the memory cell has characteristic data in initial power-up operation by the difference in transfer conductance gm between those two inverters and an ROM cell serves as even an ROM cell.

Description

[Detailed description of the invention] The present invention relates to memories, and more particularly to static RAM.

Conventionally, as shown in Fig. 1, a metallic RAM cell is composed of six M (US) transistors Q1 to QE, QDI and QD.
In the case of 2 and 9, this cell has two inverters (b)
It has a structure of a flip-flop circuit in which the input circuit is input to each other and the output is input to each other. Such a memory has the function of allowing random access operations as long as power is supplied. However, such a memory does not retain its memory once the source is disconnected.

An object of the present invention is to provide a memory that has almost the same configuration as a static RAM and is capable of holding fixed memory.

The memory according to the present invention has memory cells in which the gate inputs of tebretion type load transistors of the same size are connected in opposite directions in two inverter circuits whose inputs and outputs are cross-connected. It is characterized in that each AN cell has unique data due to a difference in transfer conductance of 9 m.

FIG. 2 shows an embodiment of a memory cell according to the present invention. Here, the first inverter is composed of a single-type load transistor Q, Dt and an enhancement input transistor QE, and a single-type load transistor QD! Enhancement input transistor QE
and a second inverter consisting of and a flip-flop by cross-connecting their input/output nodes at nodes N, , N, and a second inverter consisting of nodes N, and to, and digital y ) k 1' g +
The memory cell is constructed by providing the gate transistors q and Q of the interconnection control controlled by the word line Xi between the DI and the DI.

You can become pregnant. Here, the gate of QDt is on the source side,
The gate of t is connected to the drain side. This flip 70 tube operates as a normal RAM in normal use, but due to the difference in ym, when no data is written, the output of the first inverter is "Vcc" and the output of the second inverter is 101. 9moCVcc -v
T' When connected to the e-source side' 9 m cc
-V 7 + and the load N as in Fig. 3(a)
(The output of J8 is as shown in Figure 3. Considering a LAM cell (according to the present invention with zero order as shown in bl), the VCCO value is 1 ml of the enhancement transistor QK (up to 11).
・The output at
I > VN2 #) Finally, the data of the cell is determined by Q so that , , , and 101 are obtained.

An example of the output is shown in Figure 3). These functions will be explained using the block diagram of )tAl'l/l in FIG. 4 (a).

(bl is a load M (J8's gate connection direction is different from each other) LAN 2 is defined as l(AM 1, )LAN 2, Figure 4 (C1 is a general static) tAJl
An example of the configuration is shown below. In this configuration, a RAM cell is usually determined for each address (AO-An) by an X and Y decoder, and a RAM cell is determined for each address (AO-An).
ite (411 import) is executed. This is normal R
Perhaps this is an ead-write memory operation, but if the power supply Vcc is supplied without writing data here (in other words, in the initial state), the RAM cell corresponding to the address determined by the x, y decoder is W1. Depending on the RAM 2, the data is determined to be '11 or @01. Table 1 shows the data for the address in the configuration example of FIG. 4(c).
Therefore, the RAM cell of the present invention, in which the connection of the gate of the TEPRESSI-type load N (J8 is switched between the source and drain), can have the function of a tOM in addition to the function of a RAM. Also, RAN for the address
1. As shown in FIG. 5, the RAM2 cell can be easily used as a mask ROM by changing only the contacts, similar to the conventional RUMg production technique.

[Brief explanation of drawings]

Figure 1 shows a conventional 6-transistor static RAM cell, Figure M2 shows a 6-transistor static RAM cell according to the present invention, and Figure 3(a) shows a load M.
08 model #(bJ, (CJ is an output example with respect to Vcc, FIG. 4<aJ~ (C1 is a diagram showing a configuration example using the memory cell of the present invention, FIG. 5 is a diagram showing a configuration example using the memory cell of the present invention with a mask R)
(Explanatory diagram for making it work as a JN.
Dt...Depressi Sun M (JS0 Cow l Figure 2 sides (Give) Falcon 3 eyes Sheep 4 sides $, S Concave

Claims (1)

[Claims] Depleted, silicon type M (J8FET) on the linked side of a memory cell containing two inverter circuits whose input and output are cross-connected
By connecting the gate electrodes of the cell with the source and drain opposite to each other, the memory 0 is made to have unique data in the cell at the initial stage 1 and when the power is turned on.