JPS58107937A - チヤネル制御方式 - Google Patents

チヤネル制御方式

Info

Publication number
JPS58107937A
JPS58107937A JP56207880A JP20788081A JPS58107937A JP S58107937 A JPS58107937 A JP S58107937A JP 56207880 A JP56207880 A JP 56207880A JP 20788081 A JP20788081 A JP 20788081A JP S58107937 A JPS58107937 A JP S58107937A
Authority
JP
Japan
Prior art keywords
byte
data
mark
bytes
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56207880A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0348543B2 (enExample
Inventor
Seiichi Shimizu
誠一 清水
Masao Koyabu
小「あ」　正夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56207880A priority Critical patent/JPS58107937A/ja
Publication of JPS58107937A publication Critical patent/JPS58107937A/ja
Publication of JPH0348543B2 publication Critical patent/JPH0348543B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
JP56207880A 1981-12-22 1981-12-22 チヤネル制御方式 Granted JPS58107937A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56207880A JPS58107937A (ja) 1981-12-22 1981-12-22 チヤネル制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56207880A JPS58107937A (ja) 1981-12-22 1981-12-22 チヤネル制御方式

Publications (2)

Publication Number Publication Date
JPS58107937A true JPS58107937A (ja) 1983-06-27
JPH0348543B2 JPH0348543B2 (enExample) 1991-07-24

Family

ID=16547081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56207880A Granted JPS58107937A (ja) 1981-12-22 1981-12-22 チヤネル制御方式

Country Status (1)

Country Link
JP (1) JPS58107937A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6154555A (ja) * 1984-08-24 1986-03-18 Fujitsu Ltd チャネル処理装置
JPH04102127A (ja) * 1990-08-22 1992-04-03 Fujitsu Ltd データバッファのパリティチェック回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6154555A (ja) * 1984-08-24 1986-03-18 Fujitsu Ltd チャネル処理装置
JPH04102127A (ja) * 1990-08-22 1992-04-03 Fujitsu Ltd データバッファのパリティチェック回路

Also Published As

Publication number Publication date
JPH0348543B2 (enExample) 1991-07-24

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