JPS5810046U - Ratchet feed malfunction detection circuit - Google Patents
Ratchet feed malfunction detection circuitInfo
- Publication number
- JPS5810046U JPS5810046U JP10431181U JP10431181U JPS5810046U JP S5810046 U JPS5810046 U JP S5810046U JP 10431181 U JP10431181 U JP 10431181U JP 10431181 U JP10431181 U JP 10431181U JP S5810046 U JPS5810046 U JP S5810046U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- terminal
- input
- output
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Devices, Machine Parts, Or Other Structures Thereof (AREA)
- Reciprocating Conveyors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の回路による一実施例の斜視図。
第２図はＩＣで構成し′た本考案の回路図。第３図は送
り周期、底土時間、検出、判定、シフト等のタイミング
関係図。
１・・・・・・搬送治工具、ｌａ、 ｌｂ・・・・・
・（搬送治工具に取り付けた）反射板、２・・・・・・
ラック、３・・・・・・ラチェットツメ、４．．５・・
・・・・光電スイッチ、６・・・・・・駆動モータ、７
・・・・・・駆動カム、８・・・・・・駆動レバー、９
・・・・・・駆動シャフト、１０・・・・・・動力伝達
コマ、−１１，１２，１３・・・・・・タイミングカム
、１１ａ。
１２ａ、１３ａ・・・・・・タイミング信号、１４・・
・・・・シフト・レジスタ、［５・・・・・・第１ＡＮ
Ｄ回路、１６・・・・・・ −第２ＡＮＤ回路、１７・
・・・・・第３ＡＮＤ回路、１８・・・・・・排他的論
理和回路、１９・・・・・・フリップ・フロップ回路。FIG. 1 is a perspective view of an embodiment of the circuit of the present invention. Figure 2 is a circuit diagram of the present invention constructed from ICs. FIG. 3 is a diagram showing the timing relationship of the feed cycle, soil time, detection, judgment, shift, etc. 1... Conveyance jig, la, lb...
・Reflector plate (attached to the transport jig), 2...
Rack, 3...Ratchet claw, 4. ．． 5...
...Photoelectric switch, 6... Drive motor, 7
... Drive cam, 8... Drive lever, 9
... Drive shaft, 10... Power transmission piece, -11, 12, 13... Timing cam, 11a. 12a, 13a...timing signal, 14...
...Shift register, [5...1st AN
D circuit, 16... - 2nd AND circuit, 17.
...Third AND circuit, 18...Exclusive OR circuit, 19...Flip-flop circuit.
Claims (1)
方の端子に接続され、かつ第１ＡＮＤ回路入力側の他方
の端子に第１タイミング信号を接続し、前記第１ＡＮＤ
回路の出力端子はシフトレジスタ回路の入力端子に接続
され、前記シフト・レジスタ回路の出力端子を排他的論
理和回路の入力端子の一方に接続し、第２光電スイツチ
の出力は第２ＡＮＤ回路の入力側の一方の端子に接続さ
れ、かつ第２ＡＮＤ回路入力側の他方の端子に第１タイ
ミング信号を接続し、前記第２ＡＮＤ回路の出力は排他
的論理和回路の入力端子の残る一方の端子に接続し、前
記排他的論理和回路の出力端子は第３ＡＮＤ回路の入力
端子の一方と接続され、かつ第３ＡＮＤ回路入力端子の
他方と第２タイミングング信号を接続し、前記第３ＡＮ
Ｄ回路の出力端５子をフリップフロップ回路の入力端子
に接続し、前記シフトレジスタ回路のシフト入力端子に
第３タイミング信号を接続し、かつ前記シフトレジスタ
回路のリセット端子とフリップ・フロップ回路のリセッ
ト端子にリセット信号を接続することを特徴とするラチ
ェット送り誤動作検出回路。The output of the first photoelectric switch is connected to one terminal on the input side of the first AND circuit, and the first timing signal is connected to the other terminal on the input side of the first AND circuit.
The output terminal of the circuit is connected to the input terminal of the shift register circuit, the output terminal of the shift register circuit is connected to one of the input terminals of the exclusive OR circuit, and the output of the second photoelectric switch is connected to the input terminal of the second AND circuit. and the first timing signal is connected to one terminal of the input side of the second AND circuit, and the output of the second AND circuit is connected to the remaining one of the input terminals of the exclusive OR circuit. The output terminal of the exclusive OR circuit is connected to one of the input terminals of the third AND circuit, and the other of the input terminals of the third AND circuit is connected to the second timing signal.
An output terminal 5 of the D circuit is connected to an input terminal of a flip-flop circuit, a third timing signal is connected to a shift input terminal of the shift register circuit, and a reset terminal of the shift register circuit and a reset terminal of the flip-flop circuit are connected. A ratchet feed malfunction detection circuit characterized by connecting a reset signal to a terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10431181U JPS5810046U (en) | 1981-07-14 | 1981-07-14 | Ratchet feed malfunction detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10431181U JPS5810046U (en) | 1981-07-14 | 1981-07-14 | Ratchet feed malfunction detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5810046U true JPS5810046U (en) | 1983-01-22 |
| JPS6326339Y2 JPS6326339Y2 (en) | 1988-07-18 |
Family
ID=29898911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10431181U Granted JPS5810046U (en) | 1981-07-14 | 1981-07-14 | Ratchet feed malfunction detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5810046U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5243081U (en) * | 1975-09-22 | 1977-03-26 |
-
1981
- 1981-07-14 JP JP10431181U patent/JPS5810046U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5243081U (en) * | 1975-09-22 | 1977-03-26 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6326339Y2 (en) | 1988-07-18 |
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