JPS5793748A - Clock synchronizing circuit - Google Patents
Clock synchronizing circuitInfo
- Publication number
- JPS5793748A JPS5793748A JP55170061A JP17006180A JPS5793748A JP S5793748 A JPS5793748 A JP S5793748A JP 55170061 A JP55170061 A JP 55170061A JP 17006180 A JP17006180 A JP 17006180A JP S5793748 A JPS5793748 A JP S5793748A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- phase
- output
- frequency
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 abstract 3
- 230000010355 oscillation Effects 0.000 abstract 2
- 230000004069 differentiation Effects 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55170061A JPS5793748A (en) | 1980-12-02 | 1980-12-02 | Clock synchronizing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55170061A JPS5793748A (en) | 1980-12-02 | 1980-12-02 | Clock synchronizing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5793748A true JPS5793748A (en) | 1982-06-10 |
| JPS6357984B2 JPS6357984B2 (enrdf_load_stackoverflow) | 1988-11-14 |
Family
ID=15897896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55170061A Granted JPS5793748A (en) | 1980-12-02 | 1980-12-02 | Clock synchronizing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5793748A (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6594331B1 (en) | 1999-05-11 | 2003-07-15 | Nec Electronics Corporation | Two phase digital phase locked loop circuit |
-
1980
- 1980-12-02 JP JP55170061A patent/JPS5793748A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6594331B1 (en) | 1999-05-11 | 2003-07-15 | Nec Electronics Corporation | Two phase digital phase locked loop circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6357984B2 (enrdf_load_stackoverflow) | 1988-11-14 |
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