JPS5793720A - Output set circuit for delayed type flip-flop - Google Patents
Output set circuit for delayed type flip-flopInfo
- Publication number
- JPS5793720A JPS5793720A JP55170756A JP17075680A JPS5793720A JP S5793720 A JPS5793720 A JP S5793720A JP 55170756 A JP55170756 A JP 55170756A JP 17075680 A JP17075680 A JP 17075680A JP S5793720 A JPS5793720 A JP S5793720A
- Authority
- JP
- Japan
- Prior art keywords
- ffs
- delayed type
- outputs
- flop
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
Landscapes
- Electronic Switches (AREA)
Abstract
PURPOSE:To prevent the coincidence of outputs of all FFs at the application of power supply, by setting the output of at least one FF out of a plurality of delayed type FFs to a different output from other FFs compulsively. CONSTITUTION:Outputs X1-X5 are at L when channel buttons 7-11 are depressed, and the signal at L level becomes an address designation signal of a preset memory to select corresponding channels. In this case, all delayed type FFs 1-5 are at L at the application of power supply, then no selected channel can be determined. Thus, a control circuit 6 makes H only for the output X5 of the channel 5 even if the outputs X1-X5 are all at L at the application of power supply, allowing to prevent the coincidence of the outputs X1-X5of the FFs.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55170756A JPS5793720A (en) | 1980-12-02 | 1980-12-02 | Output set circuit for delayed type flip-flop |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55170756A JPS5793720A (en) | 1980-12-02 | 1980-12-02 | Output set circuit for delayed type flip-flop |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5793720A true JPS5793720A (en) | 1982-06-10 |
JPH025337B2 JPH025337B2 (en) | 1990-02-01 |
Family
ID=15910794
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55170756A Granted JPS5793720A (en) | 1980-12-02 | 1980-12-02 | Output set circuit for delayed type flip-flop |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5793720A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015037265A (en) * | 2013-08-14 | 2015-02-23 | ラピスセミコンダクタ株式会社 | Semiconductor device and power supply control method |
-
1980
- 1980-12-02 JP JP55170756A patent/JPS5793720A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015037265A (en) * | 2013-08-14 | 2015-02-23 | ラピスセミコンダクタ株式会社 | Semiconductor device and power supply control method |
Also Published As
Publication number | Publication date |
---|---|
JPH025337B2 (en) | 1990-02-01 |
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