JPS5787218A - Load driving circuit - Google Patents

Load driving circuit

Info

Publication number
JPS5787218A
JPS5787218A JP55162892A JP16289280A JPS5787218A JP S5787218 A JPS5787218 A JP S5787218A JP 55162892 A JP55162892 A JP 55162892A JP 16289280 A JP16289280 A JP 16289280A JP S5787218 A JPS5787218 A JP S5787218A
Authority
JP
Japan
Prior art keywords
signal
voltage
pulse width
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55162892A
Other languages
Japanese (ja)
Inventor
Susumu Sueyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp, Pioneer Electronic Corp filed Critical Pioneer Corp
Priority to JP55162892A priority Critical patent/JPS5787218A/en
Publication of JPS5787218A publication Critical patent/JPS5787218A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the power cunsumption and improve the power conversion efficiency, by subjecting and AC voltage of a square waveform to pulse width modulation in accordance with an input signal and by driving a load by a signal obtained by integrating this output.
CONSTITUTION: An AC voltage V3 of a square waveform which is the output of a square wave voltage generating circuit 1 is modulated by a pulse width corresponding to an input voltage vi in a pulse width modulating means 8, and the output passes through an integrating means 9 of an LPF constitution of drive a load RL such as a speaker. Voltages of positive and negative equal levels appear alternately in respect to the voltage V3, and a triangular signal is generated in a modulation signal generating circuit 11 of the means 8, and the input signal vi is sampled by this signal to generate a modulation signal of a pulse width corresponding to the signal vi, and a switching element 10 is controlled to subject the voltage V3 to pulse width modulation. The output of the circuit 11 has a frequency twice as high as the frequency of the voltage V3 when the signal vi is zero, and the width of positive pulses of the input of the means 9 becomes wider according as the signal vi becomes higher than zero, and the width of negative pulses becomes wider according as the signal vi becomes lower then zero. This signal becomes an analogue signal in the means 9 to drive the load R.
COPYRIGHT: (C)1982,JPO&Japio
JP55162892A 1980-11-19 1980-11-19 Load driving circuit Pending JPS5787218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55162892A JPS5787218A (en) 1980-11-19 1980-11-19 Load driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55162892A JPS5787218A (en) 1980-11-19 1980-11-19 Load driving circuit

Publications (1)

Publication Number Publication Date
JPS5787218A true JPS5787218A (en) 1982-05-31

Family

ID=15763228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55162892A Pending JPS5787218A (en) 1980-11-19 1980-11-19 Load driving circuit

Country Status (1)

Country Link
JP (1) JPS5787218A (en)

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