JPS5785157A - Arithmetic device - Google Patents

Arithmetic device

Info

Publication number
JPS5785157A
JPS5785157A JP16040080A JP16040080A JPS5785157A JP S5785157 A JPS5785157 A JP S5785157A JP 16040080 A JP16040080 A JP 16040080A JP 16040080 A JP16040080 A JP 16040080A JP S5785157 A JPS5785157 A JP S5785157A
Authority
JP
Japan
Prior art keywords
data
hexadecimal
key
output
operating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16040080A
Other languages
Japanese (ja)
Inventor
Kazuya Kitamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Facom Corp
Original Assignee
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Facom Corp filed Critical Fuji Facom Corp
Priority to JP16040080A priority Critical patent/JPS5785157A/en
Publication of JPS5785157A publication Critical patent/JPS5785157A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/02—Details

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Calculators And Similar Devices (AREA)

Abstract

PURPOSE:To execute an optional n-scale operation in case of a minicomputer, as well, by providing a key for designating an operation form, and switching an operation method in accordance with a state designated by this designation key. CONSTITUTION:When hexadecimal notation is designated and switched by a switch SW, its output starts a hexadecimal operating circuit PCI, applies a logical ''0'' signal to a decimal operating circuit through an inverter, and makes an operation output of the circuit PCO invalid. Subsequently, when one of the keys corresponding to numerical data of a data key DK is selected and depressed, a code signal corresponding to the data is outputted by a decoder DC, and this output is provided to a character generator CG through an OR gate 01 and also is stored in an input register IR. The code supplied to the generator CG outputs a hexadecimal data pattern to be displayed, stores it in a display register DR, and displays it on an display device DP.
JP16040080A 1980-11-14 1980-11-14 Arithmetic device Pending JPS5785157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16040080A JPS5785157A (en) 1980-11-14 1980-11-14 Arithmetic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16040080A JPS5785157A (en) 1980-11-14 1980-11-14 Arithmetic device

Publications (1)

Publication Number Publication Date
JPS5785157A true JPS5785157A (en) 1982-05-27

Family

ID=15714119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16040080A Pending JPS5785157A (en) 1980-11-14 1980-11-14 Arithmetic device

Country Status (1)

Country Link
JP (1) JPS5785157A (en)

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