JPS56127265A - Electronic calculator - Google Patents
Electronic calculatorInfo
- Publication number
- JPS56127265A JPS56127265A JP2997480A JP2997480A JPS56127265A JP S56127265 A JPS56127265 A JP S56127265A JP 2997480 A JP2997480 A JP 2997480A JP 2997480 A JP2997480 A JP 2997480A JP S56127265 A JPS56127265 A JP S56127265A
- Authority
- JP
- Japan
- Prior art keywords
- key
- shunting
- data
- register
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/02—Digital computers in general; Data processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Calculators And Similar Devices (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To know the number of data shunting registers that are used presently for a small-size electronic calculator which performs the multiplication/division in preference to the addition/substraction, by displaying the using condition of the data shunting register through an operation of a specified key. CONSTITUTION:With operation of a key, the key input part 10 transmits the corresponding signal to the operation control part 11. When the control part 11 decides a necessity of shunt for the midway result with operation of both the multiplication and division keys of the part 10, the signal 101 is transmitted to the inputs of the OR gate 14 and AND gate 72. With operation of the SP key, the signal 105 is transmitted to the inverter 16 and AND gate 18 from the part 11. Thus a switching is given between the data of the register 21 and the information data of the shunting register monitor signal generating circuit for a display 12. Thus the using condition of the data shunting register is displayed with operation of the SP key to know the number of shunting registers that are used presently.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2997480A JPS56127265A (en) | 1980-03-10 | 1980-03-10 | Electronic calculator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2997480A JPS56127265A (en) | 1980-03-10 | 1980-03-10 | Electronic calculator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56127265A true JPS56127265A (en) | 1981-10-05 |
Family
ID=12290923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2997480A Pending JPS56127265A (en) | 1980-03-10 | 1980-03-10 | Electronic calculator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56127265A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5469029A (en) * | 1977-11-11 | 1979-06-02 | Casio Comput Co Ltd | Display system for brackets level number |
-
1980
- 1980-03-10 JP JP2997480A patent/JPS56127265A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5469029A (en) * | 1977-11-11 | 1979-06-02 | Casio Comput Co Ltd | Display system for brackets level number |
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