JPS5776986A - Signal processing circuit - Google Patents

Signal processing circuit

Info

Publication number
JPS5776986A
JPS5776986A JP55153286A JP15328680A JPS5776986A JP S5776986 A JPS5776986 A JP S5776986A JP 55153286 A JP55153286 A JP 55153286A JP 15328680 A JP15328680 A JP 15328680A JP S5776986 A JPS5776986 A JP S5776986A
Authority
JP
Japan
Prior art keywords
frame
signal
video signal
input
signal processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55153286A
Other languages
Japanese (ja)
Inventor
Isao Tofuku
Hiroyuki Ishizaki
Yoshinori Tsujino
Shoji Doi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55153286A priority Critical patent/JPS5776986A/en
Publication of JPS5776986A publication Critical patent/JPS5776986A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Closed-Circuit Television Systems (AREA)
  • Facsimile Image Signal Circuits (AREA)
  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To obtain a video signal having high SN ratio, by converting an input video signal to a binary picture through threshold processing at first, performing multiplex addition at each frame and performing threshold value processing to the output again. CONSTITUTION:An input signal of the 1st frame is digitized at an A/D converter 2 and applied to an input terminal 15 of a comparator 14, and it is compared with a voltage determining the 1st slice level for binarization. This binarized 1st frame signal is stored in a frame memory 4. This stored signal is applied to the 2nd input terminal 8 of an adder via a path 5 for multiplex addition. This video signal of multiplex addition is applied to the 2nd comparator 10 and compared with the 2nd slice level for binarization again.
JP55153286A 1980-10-30 1980-10-30 Signal processing circuit Pending JPS5776986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55153286A JPS5776986A (en) 1980-10-30 1980-10-30 Signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55153286A JPS5776986A (en) 1980-10-30 1980-10-30 Signal processing circuit

Publications (1)

Publication Number Publication Date
JPS5776986A true JPS5776986A (en) 1982-05-14

Family

ID=15559148

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55153286A Pending JPS5776986A (en) 1980-10-30 1980-10-30 Signal processing circuit

Country Status (1)

Country Link
JP (1) JPS5776986A (en)

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