JPS5775585A - Motor speed control system - Google Patents
Motor speed control systemInfo
- Publication number
- JPS5775585A JPS5775585A JP55150059A JP15005980A JPS5775585A JP S5775585 A JPS5775585 A JP S5775585A JP 55150059 A JP55150059 A JP 55150059A JP 15005980 A JP15005980 A JP 15005980A JP S5775585 A JPS5775585 A JP S5775585A
- Authority
- JP
- Japan
- Prior art keywords
- time
- output signal
- error amplifier
- firing
- firing phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
- H02P7/03—Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Electric Motors In General (AREA)
- Control Of Direct Current Motors (AREA)
Abstract
PURPOSE:To suppress excessive current in addition to the time shortcircuit at the switching time by clampling the firing phase at a predetermined time when the output signal of an error amplifier is code converted. CONSTITUTION:When a speed command S1 is switched from positive to negative, the output signal S3 of an adder 41 is inverted, and the output signal of an error amplifier 42 is also inverted. Thus, an output signal S5 is not delivered from a code discriminator 44 during a predetermined period of time, thereby inhibiting the firing of a thyristor. Simultaneously, an absolute value limiter 48 is operated by a clamping command signal S10 during the time of this time plus the predetermined period of time. An absolute value circuit 43 is operated by the operation of the limiter 48, the output of the circuit 43 and hence the firing phase is limited to the limiting value alpha0 determined in response to the rotating speed of the motor 1, and accordingly the firing phase does not exceed alpha0 even when the output signal S4 of an error amplifier 42 is increased.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55150059A JPS5775585A (en) | 1980-10-28 | 1980-10-28 | Motor speed control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55150059A JPS5775585A (en) | 1980-10-28 | 1980-10-28 | Motor speed control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5775585A true JPS5775585A (en) | 1982-05-12 |
JPS6223551B2 JPS6223551B2 (en) | 1987-05-23 |
Family
ID=15488605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55150059A Granted JPS5775585A (en) | 1980-10-28 | 1980-10-28 | Motor speed control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5775585A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4828914A (en) * | 1971-08-20 | 1973-04-17 | ||
JPS5574389A (en) * | 1978-11-27 | 1980-06-04 | Fanuc Ltd | Drive circuit for permanent magnet type dc motor |
-
1980
- 1980-10-28 JP JP55150059A patent/JPS5775585A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4828914A (en) * | 1971-08-20 | 1973-04-17 | ||
JPS5574389A (en) * | 1978-11-27 | 1980-06-04 | Fanuc Ltd | Drive circuit for permanent magnet type dc motor |
Also Published As
Publication number | Publication date |
---|---|
JPS6223551B2 (en) | 1987-05-23 |
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