JPS5768946A - Relay device - Google Patents

Relay device

Info

Publication number
JPS5768946A
JPS5768946A JP55144504A JP14450480A JPS5768946A JP S5768946 A JPS5768946 A JP S5768946A JP 55144504 A JP55144504 A JP 55144504A JP 14450480 A JP14450480 A JP 14450480A JP S5768946 A JPS5768946 A JP S5768946A
Authority
JP
Japan
Prior art keywords
counter
count value
count
value
rom4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55144504A
Other languages
Japanese (ja)
Inventor
Harunobu Kadota
Shuichi Okazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP55144504A priority Critical patent/JPS5768946A/en
Publication of JPS5768946A publication Critical patent/JPS5768946A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To perform suitable sampling, by presetting the correction value increased/decreased in the relation of almost cube to the count of a counter at the polarity changing point of a reception data, in a relay device identifying and reproducing the code of reception data. CONSTITUTION:An input data converted to a logic level at a line receiver 1 is detected for the polarity changing point at a differentiation circuit 2, and the output is outputted to a counter 3 and a ROM4. The counter 3 counts clocks from a clock pulse generator 7 and presets a value corresponding to the count value from the list stored in the ROM4 to a counter 3 with a signal from the circuit 2. Values storing the correction value increased/decreased in the relation of about cube to the count value, subtracted from the count value to the count value are stored in the ROM4 and the counter 3 is preset to about intermediate count value of the counter at the polarity changing point. The counter 3 outputs a carry pulse to the FF5 when the count is made to the specified value, the FF5 identifies the output level of the receiver 1 and outputs it to a line driver 6, and the driver 6 converts it to the line level.
JP55144504A 1980-10-17 1980-10-17 Relay device Pending JPS5768946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55144504A JPS5768946A (en) 1980-10-17 1980-10-17 Relay device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55144504A JPS5768946A (en) 1980-10-17 1980-10-17 Relay device

Publications (1)

Publication Number Publication Date
JPS5768946A true JPS5768946A (en) 1982-04-27

Family

ID=15363892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55144504A Pending JPS5768946A (en) 1980-10-17 1980-10-17 Relay device

Country Status (1)

Country Link
JP (1) JPS5768946A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62115940A (en) * 1985-12-12 1987-05-27 Oki Electric Ind Co Ltd Repeater
EP0261428A2 (en) * 1986-08-27 1988-03-30 Nec Corporation Clock recovering device
JPH0493288U (en) * 1990-12-28 1992-08-13

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62115940A (en) * 1985-12-12 1987-05-27 Oki Electric Ind Co Ltd Repeater
EP0261428A2 (en) * 1986-08-27 1988-03-30 Nec Corporation Clock recovering device
JPH0493288U (en) * 1990-12-28 1992-08-13

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