JPS5763977A - Receiver of character broadcast - Google Patents
Receiver of character broadcastInfo
- Publication number
- JPS5763977A JPS5763977A JP14021180A JP14021180A JPS5763977A JP S5763977 A JPS5763977 A JP S5763977A JP 14021180 A JP14021180 A JP 14021180A JP 14021180 A JP14021180 A JP 14021180A JP S5763977 A JPS5763977 A JP S5763977A
- Authority
- JP
- Japan
- Prior art keywords
- character
- circuit
- signal
- channel
- video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Systems (AREA)
Abstract
PURPOSE:To simplify the constitution of a character receiver, by securing the reception of the video broadcast and the character multiplex broadcast signal of different channels with the time-division use of a pair of receiving circuit parts. CONSTITUTION:Plural TV signals containing the TV signal multiplexed by the character broadcast are received by a TV receiving circuit 10, and the channels displaying the image and characters are selected among those TV signals through channel selection voltage generating circuits 22A and 22B. At the same time, the character broadcast signal is extracted out of the TV signal through a character decoder 32, and the phase difference is detected by a phase difference detecting circuit 33 between the video channel and the character channel TV signal. This detected phase difference is stored in the 1st memory circuit 34, and the receiving channel of the circuit 10 is switched to the character channel from the video channel by a switch control circuit 35 for a prescribed period of time and based on the output of the circuit 34 and the synchronous signal of the video signal. Then the video signal is recorded and reproduced through the 2nd memory circuit 23 during the character channel to be synthesized at a synthesizing circuit 43.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14021180A JPS5763977A (en) | 1980-10-07 | 1980-10-07 | Receiver of character broadcast |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14021180A JPS5763977A (en) | 1980-10-07 | 1980-10-07 | Receiver of character broadcast |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5763977A true JPS5763977A (en) | 1982-04-17 |
Family
ID=15263497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14021180A Pending JPS5763977A (en) | 1980-10-07 | 1980-10-07 | Receiver of character broadcast |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5763977A (en) |
-
1980
- 1980-10-07 JP JP14021180A patent/JPS5763977A/en active Pending
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