JPS55100783A - Two-screen display television receiver - Google Patents

Two-screen display television receiver

Info

Publication number
JPS55100783A
JPS55100783A JP839079A JP839079A JPS55100783A JP S55100783 A JPS55100783 A JP S55100783A JP 839079 A JP839079 A JP 839079A JP 839079 A JP839079 A JP 839079A JP S55100783 A JPS55100783 A JP S55100783A
Authority
JP
Japan
Prior art keywords
circuit
channel
main
sub
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP839079A
Other languages
Japanese (ja)
Inventor
Yoshitaka Omori
Seiji Sumi
Koji Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP839079A priority Critical patent/JPS55100783A/en
Publication of JPS55100783A publication Critical patent/JPS55100783A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to discriminate clearly between images of main and sub channels, by projecting any other sub channel than a main channel that a user is watching at part of a television screen while encircling it with a frame.
CONSTITUTION: A broadcasting wave arriving from antenna 4 is led to tuners 5 and 7 for main and sub channels by way of distributor 5. A signal of the sub channel is detected by detector 11 and then written in memory circuit 13 by a synchronizing signal separated by synchronous separator circuit 10. A main-channel signal is applied to gate circuit 14 and synchronous separator circuit 9 via detector 8. A main-channel synchronizing signal obtained by synchronous separator circuit 9 reads the sub-channel signal in memory circuit 13 and it is sent out to synthesizer circuit 17. Control circuit 12 exercises control over the read and write of memory circuit 13 and also controls frame-pattern generating circuit 15. Video amplifier circuit 16 projects an image of the main channel with a frame from gate circuit 14 on color Braun tube 18.
COPYRIGHT: (C)1980,JPO&Japio
JP839079A 1979-01-26 1979-01-26 Two-screen display television receiver Pending JPS55100783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP839079A JPS55100783A (en) 1979-01-26 1979-01-26 Two-screen display television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP839079A JPS55100783A (en) 1979-01-26 1979-01-26 Two-screen display television receiver

Publications (1)

Publication Number Publication Date
JPS55100783A true JPS55100783A (en) 1980-07-31

Family

ID=11691868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP839079A Pending JPS55100783A (en) 1979-01-26 1979-01-26 Two-screen display television receiver

Country Status (1)

Country Link
JP (1) JPS55100783A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157176A (en) * 1987-07-28 1989-06-20 Sanyo Electric Co Ltd Digital television receiver and data processor to be used by receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01157176A (en) * 1987-07-28 1989-06-20 Sanyo Electric Co Ltd Digital television receiver and data processor to be used by receiver

Similar Documents

Publication Publication Date Title
US4405946A (en) Television signal converting apparatus providing an on-screen tuning display
JPS54105920A (en) Picture display device
TW351901B (en) Signal swap apparatus for a television receiver having an HDTV main picture signal processor and an NTSC Pix-in-Pix signal processor
KR850003489A (en) TV receiver with auxiliary information on-screen display
JPS54112122A (en) Picture display unit
JPS55100783A (en) Two-screen display television receiver
JPS54156420A (en) Interlace control circuit for television receivers
JPS5647171A (en) Television receiver
JPS54159815A (en) Television receiver
JPS5477521A (en) Television picture receiver
JPS593662Y2 (en) television receiver
JPS56120276A (en) Television receiver for multichannel simultaneous display
JPS56152383A (en) Television receiver for display on plural screens
EP0695086A3 (en) Method for transmitting a television signal, an accompanying signal and a control signal for displaying as a large or small image
JPS54125921A (en) Color television picture receiver
JPS54146921A (en) Television receiver with picture recording device
JPS5237705A (en) Tuner unit of television receiver
JPS5453823A (en) Television receiver
JPS5574273A (en) Television receiver
JPS5296823A (en) External signal coupling unit for television receiver
JPH0746847B2 (en) Television receiver
JPS5765971A (en) Receiving device for multiplexed information
JPS54152426A (en) Multipurpose television receiver
JPS54156421A (en) Video signal sampling method for small picture in television receivers
JPS5264223A (en) Tv receiver