JPS5754405A - Frequency modulation circuit - Google Patents

Frequency modulation circuit

Info

Publication number
JPS5754405A
JPS5754405A JP12950680A JP12950680A JPS5754405A JP S5754405 A JPS5754405 A JP S5754405A JP 12950680 A JP12950680 A JP 12950680A JP 12950680 A JP12950680 A JP 12950680A JP S5754405 A JPS5754405 A JP S5754405A
Authority
JP
Japan
Prior art keywords
output
frequency modulation
low
frequency
surely
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12950680A
Other languages
Japanese (ja)
Inventor
Shoichi Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12950680A priority Critical patent/JPS5754405A/en
Publication of JPS5754405A publication Critical patent/JPS5754405A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03C—MODULATION
    • H03C3/00—Angle modulation

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To enable frequency modulation at a comparatively lower frequency band, by converting a digital quantity once into an analog quanity and controlling the advanced time of a binary counter through the comparison with converted voltage, in a low frequency modulation circuit used for telephone lines. CONSTITUTION:A binary counter B starts advancing through the production of pulses, and an output B is in D/A conversion C and an analog quantity proportional to an intput digital quantity can be outputted H. This is compared D with an input terminal voltage and an output I is changed at the moment of crossing. This change triggers a monostable multivibrator E, resets the counter B surely and inverts an FF circuit F surely. When harmonics are removed from an output K through an LRFG, a sinusoidal wave L is obtained. Thus, when an input voltage decrease, since the output of comparator is changed while the output of D/A conversion is low, the output frequency is increased, and the output frequency is low through the increased input voltage, allowing frequency modulation at a very low frequency band.
JP12950680A 1980-09-18 1980-09-18 Frequency modulation circuit Pending JPS5754405A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12950680A JPS5754405A (en) 1980-09-18 1980-09-18 Frequency modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12950680A JPS5754405A (en) 1980-09-18 1980-09-18 Frequency modulation circuit

Publications (1)

Publication Number Publication Date
JPS5754405A true JPS5754405A (en) 1982-03-31

Family

ID=15011167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12950680A Pending JPS5754405A (en) 1980-09-18 1980-09-18 Frequency modulation circuit

Country Status (1)

Country Link
JP (1) JPS5754405A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425308U (en) * 1990-06-25 1992-02-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0425308U (en) * 1990-06-25 1992-02-28

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