JPS57501984A - - Google Patents

Info

Publication number
JPS57501984A
JPS57501984A JP57500288A JP50028882A JPS57501984A JP S57501984 A JPS57501984 A JP S57501984A JP 57500288 A JP57500288 A JP 57500288A JP 50028882 A JP50028882 A JP 50028882A JP S57501984 A JPS57501984 A JP S57501984A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57500288A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS57501984A publication Critical patent/JPS57501984A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/923—Active solid-state devices, e.g. transistors, solid-state diodes with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
JP57500288A 1980-12-12 1981-12-02 Pending JPS57501984A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/215,975 US4393464A (en) 1980-12-12 1980-12-12 Chip topography for integrated circuit communication controller

Publications (1)

Publication Number Publication Date
JPS57501984A true JPS57501984A (ja) 1982-11-04

Family

ID=22805150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57500288A Pending JPS57501984A (ja) 1980-12-12 1981-12-02

Country Status (6)

Country Link
US (1) US4393464A (ja)
EP (1) EP0066605B1 (ja)
JP (1) JPS57501984A (ja)
CA (1) CA1157952A (ja)
DE (1) DE3176926D1 (ja)
WO (1) WO1982002102A1 (ja)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4543646A (en) * 1980-06-05 1985-09-24 Western Digital Corporation Chip topography for MOS Data Encryption Standard circuit
US4514799A (en) * 1981-02-24 1985-04-30 Bell & Howell Company Bus system architecture and microprocessor system
US4449202A (en) * 1981-12-04 1984-05-15 Ncr Corporation Full duplex integrated circuit communication controller
US4534011A (en) * 1982-02-02 1985-08-06 International Business Machines Corporation Peripheral attachment interface for I/O controller having cycle steal and off-line modes
US4511914A (en) * 1982-07-01 1985-04-16 Motorola, Inc. Power bus routing for providing noise isolation in gate arrays
US4611326A (en) * 1983-03-28 1986-09-09 Digital Equipment Corporation Circuitry for identifying the validity of received data words
US4549262A (en) * 1983-06-20 1985-10-22 Western Digital Corporation Chip topography for a MOS disk memory controller circuit
US4649474A (en) * 1983-09-23 1987-03-10 Western Digital Corporation Chip topography for a MOS disk memory controller circuit
GB8329510D0 (en) * 1983-11-04 1983-12-07 Inmos Ltd Computer apparatus
JPS60101951A (ja) * 1983-11-08 1985-06-06 Sanyo Electric Co Ltd ゲ−トアレイ
US4667321A (en) * 1983-11-14 1987-05-19 Tandem Computers Incorporated Input-output multiplexer-demultiplexer communications channel
CA1242803A (en) * 1984-12-27 1988-10-04 Nobuhisa Watanabe Microprocessor with option area facilitating interfacing with peripheral devices
US5165086A (en) * 1985-02-20 1992-11-17 Hitachi, Ltd. Microprocessor chip using two-level metal lines technology
US4751634A (en) * 1985-06-14 1988-06-14 International Business Machines Corporation Multiple port communications adapter apparatus
US4837677A (en) * 1985-06-14 1989-06-06 International Business Machines Corporation Multiple port service expansion adapter for a communications controller
US4720828A (en) * 1986-03-31 1988-01-19 Wang Laboratories, Inc. I/o handler
JPS62251951A (ja) * 1986-04-22 1987-11-02 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション デ−タ処理システム
JPS63118856A (ja) * 1986-11-06 1988-05-23 Nec Corp シリアル・バス・インタフエ−ス回路
JP2569053B2 (ja) * 1987-06-26 1997-01-08 キヤノン株式会社 イメ−ジセンサ
US5010480A (en) * 1987-07-21 1991-04-23 Dsp Technology Communication interface for interfacing a data bus of a computer to a high speed bipolar communication system
BE1001383A7 (fr) * 1987-12-07 1989-10-17 Electronique Et Telecomm Bell Dispositif a acces multiples.
GB8728902D0 (en) * 1987-12-10 1988-01-27 Secr Defence Microcomputer circuits
JP2570845B2 (ja) * 1988-05-27 1997-01-16 セイコーエプソン株式会社 情報処理装置
US5237660A (en) * 1988-12-27 1993-08-17 Ncr Corporation Control method and apparatus for controlling the data flow rate in a FIFO memory, for synchronous SCSI data transfers
US5263141A (en) * 1989-01-31 1993-11-16 Brother Kogyo Kabushiki Kaisha Microprocessor with an exclusive address terminal for selecting at least one part of a peripheral device
EP0485594A4 (en) * 1990-05-30 1995-02-01 Adaptive Solutions Inc Mechanism providing concurrent computational/communications in simd architecture
JPH04340118A (ja) * 1990-06-05 1992-11-26 Seiko Epson Corp コンピュータ
US5309561A (en) * 1990-09-28 1994-05-03 Tandem Computers Incorporated Synchronous processor unit with interconnected, separately clocked processor sections which are automatically synchronized for data transfer operations
US5226124A (en) * 1991-06-05 1993-07-06 Ambrosia Microcomputer Products, Inc. Communication interface between a radio control transmitter and a computer data bus
WO1993021575A1 (en) * 1992-04-13 1993-10-28 Seiko Epson Corporation A high density buffer memory architecture and method
US5752216A (en) * 1994-07-06 1998-05-12 Dimensions International, Inc. Non-intrusive data interface system for air traffic control
US5784291A (en) * 1994-12-22 1998-07-21 Texas Instruments, Incorporated CPU, memory controller, bus bridge integrated circuits, layout structures, system and methods
SE9500525L (sv) * 1995-02-13 1996-08-14 Essnet Ab Anordning för seriell dataöverföring
US6049136A (en) * 1998-06-03 2000-04-11 Hewlett-Packard Company Integrated circuit having unique lead configuration
JP2001175611A (ja) * 1999-12-17 2001-06-29 Nec Corp プロセッサ間通信インタフェース回路及び半導体集積回路装置
US7265356B2 (en) * 2004-11-29 2007-09-04 The University Of Chicago Image-guided medical intervention apparatus and method
US11749572B2 (en) * 2020-05-19 2023-09-05 Macronix International Co., Ltd. Testing bonding pads for chiplet systems

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3968478A (en) * 1974-10-30 1976-07-06 Motorola, Inc. Chip topography for MOS interface circuit
US4021781A (en) * 1974-11-19 1977-05-03 Texas Instruments Incorporated Virtual ground read-only-memory for electronic calculator or digital processor
US3975712A (en) * 1975-02-18 1976-08-17 Motorola, Inc. Asynchronous communication interface adaptor
US4071887A (en) * 1975-10-30 1978-01-31 Motorola, Inc. Synchronous serial data adaptor
US4125854A (en) * 1976-12-02 1978-11-14 Mostek Corporation Symmetrical cell layout for static RAM
US4144561A (en) * 1977-07-08 1979-03-13 Xerox Corporation Chip topography for MOS integrated circuitry microprocessor chip
US4278897A (en) * 1978-12-28 1981-07-14 Fujitsu Limited Large scale semiconductor integrated circuit device

Also Published As

Publication number Publication date
EP0066605A1 (en) 1982-12-15
EP0066605B1 (en) 1988-11-02
EP0066605A4 (en) 1985-12-11
CA1157952A (en) 1983-11-29
DE3176926D1 (en) 1988-12-08
US4393464A (en) 1983-07-12
WO1982002102A1 (en) 1982-06-24

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