JPS5750005A - On and off ratio controller - Google Patents
On and off ratio controllerInfo
- Publication number
- JPS5750005A JPS5750005A JP12423980A JP12423980A JPS5750005A JP S5750005 A JPS5750005 A JP S5750005A JP 12423980 A JP12423980 A JP 12423980A JP 12423980 A JP12423980 A JP 12423980A JP S5750005 A JPS5750005 A JP S5750005A
- Authority
- JP
- Japan
- Prior art keywords
- output
- counter
- flip
- flop
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B11/00—Automatic controllers
- G05B11/01—Automatic controllers electric
- G05B11/26—Automatic controllers electric in which the output signal is a pulse-train
- G05B11/28—Automatic controllers electric in which the output signal is a pulse-train using pulse-height modulation; using pulse-width modulation
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Feedback Control In General (AREA)
Abstract
PURPOSE:To exercise on-off ratio control with simple constitution by setting a bistable circuit with a counter output which varies in contents at constant intervals of time and resetting it with the output of a comparison between the counter output and another counter output. CONSTITUTION:A counter 1 counts a clock signal 1 and its output is sent to a comparator 3 and a decoder 5. The decoder 5, when counter outputs B1-B3 are all Os, generates an output to set a flip-flop 4. A comparator 2 is applied with the output of a counter 2 and, when the outputs of both the counters are coincident with each other, resets the flip-flop 4 with an output pulse D. A flip-flop output F is therefore an on-off output having a duty corresponding to the data of the counter 2. When a control signal E has a level 1, the counter 2 counts a clock G and the switching of the duty is facilitated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12423980A JPS5750005A (en) | 1980-09-08 | 1980-09-08 | On and off ratio controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12423980A JPS5750005A (en) | 1980-09-08 | 1980-09-08 | On and off ratio controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5750005A true JPS5750005A (en) | 1982-03-24 |
Family
ID=14880403
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12423980A Pending JPS5750005A (en) | 1980-09-08 | 1980-09-08 | On and off ratio controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5750005A (en) |
-
1980
- 1980-09-08 JP JP12423980A patent/JPS5750005A/en active Pending
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