JPS5748874A - Video signal processing circuit - Google Patents
Video signal processing circuitInfo
- Publication number
- JPS5748874A JPS5748874A JP55123454A JP12345480A JPS5748874A JP S5748874 A JPS5748874 A JP S5748874A JP 55123454 A JP55123454 A JP 55123454A JP 12345480 A JP12345480 A JP 12345480A JP S5748874 A JPS5748874 A JP S5748874A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- voltage
- pinch
- source
- input voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 101100180304 Arabidopsis thaliana ISS1 gene Proteins 0.000 abstract 1
- 101100519257 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) PDR17 gene Proteins 0.000 abstract 1
- 101100042407 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SFB2 gene Proteins 0.000 abstract 1
- 238000001514 detection method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
- H04N5/202—Gamma control
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
- Transforming Electric Information Into Light Information (AREA)
Abstract
PURPOSE:To achieve a simple gamma compensation cancel circuit with good frequency characteristics, less power consumption, by using the square characteristic of a FET and rejecting the effect of offset of the transistor. CONSTITUTION:FETs TR4, 5 are N channel junction type formed on the same board and the TR5 is used for pinch-off voltage detection. The drain of the FET TR5 is connected to a positive power supply VDD, and the gate is connected to ground at which the input voltage V1 is at black level, and a minute current source ISS1 is inserted between the source of the FET TR5 and a negative power supply -Vss, and a voltage VGS between the gate and the source of the FET TR5 is biased to the pinch-off voltage Vp. Thus, the FET TR4 is biased so that it is just the pinch-off voltage when the input voltage V1 is zero, and the drain current ID4 of the FET TR4 against the input voltage V1 has a square characteristic without offset- voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55123454A JPS5748874A (en) | 1980-09-08 | 1980-09-08 | Video signal processing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55123454A JPS5748874A (en) | 1980-09-08 | 1980-09-08 | Video signal processing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5748874A true JPS5748874A (en) | 1982-03-20 |
Family
ID=14861007
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55123454A Pending JPS5748874A (en) | 1980-09-08 | 1980-09-08 | Video signal processing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5748874A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5299000A (en) * | 1992-06-17 | 1994-03-29 | Zenith Electronics Corp. | Video white signal compression and peaking |
-
1980
- 1980-09-08 JP JP55123454A patent/JPS5748874A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5299000A (en) * | 1992-06-17 | 1994-03-29 | Zenith Electronics Corp. | Video white signal compression and peaking |
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