JPS5747683A - Printer - Google Patents

Printer

Info

Publication number
JPS5747683A
JPS5747683A JP55122187A JP12218780A JPS5747683A JP S5747683 A JPS5747683 A JP S5747683A JP 55122187 A JP55122187 A JP 55122187A JP 12218780 A JP12218780 A JP 12218780A JP S5747683 A JPS5747683 A JP S5747683A
Authority
JP
Japan
Prior art keywords
signal
state
motor
output
anomaly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55122187A
Other languages
Japanese (ja)
Inventor
Takashi Tsunoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP55122187A priority Critical patent/JPS5747683A/en
Publication of JPS5747683A publication Critical patent/JPS5747683A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To remove the anomaly of printing operation by a method in which an anomaly of operation is detected on the basis of signal generated as a motor turns and a driving signal for the motor is soon stopped immediately after being detected.
CONSTITUTION: A printer is turned ON, a motor driving signal A from a driving control circuit S is made to the state of "1", a motor MT is turned to generate signal T1 from a pulse generator PG, and even the output T2 of retrigger type one- shot multivibrator OS is made to the state of "1". When an anomaly occurs in the printer, signal T1 from PG is not generated, and when time lapses by as much as time constant t, output T2 of OS is changed to the state of "0", and the output is offered through an interface buffer VIA and line IRQ to a central arithmetic circuit CPU. At this time, in CPU, control signal D2 is made to the state of "0", the supply of signal A to MT is stopped, and the driving signal D3 of solenoid is also stopped.
COPYRIGHT: (C)1982,JPO&Japio
JP55122187A 1980-09-03 1980-09-03 Printer Pending JPS5747683A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55122187A JPS5747683A (en) 1980-09-03 1980-09-03 Printer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55122187A JPS5747683A (en) 1980-09-03 1980-09-03 Printer

Publications (1)

Publication Number Publication Date
JPS5747683A true JPS5747683A (en) 1982-03-18

Family

ID=14829721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55122187A Pending JPS5747683A (en) 1980-09-03 1980-09-03 Printer

Country Status (1)

Country Link
JP (1) JPS5747683A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160263U (en) * 1983-04-12 1984-10-26 マックス株式会社 electric printer
JPS60170480A (en) * 1984-02-13 1985-09-03 Fuji Xerox Co Ltd Speed controller for motor
JPH02295749A (en) * 1989-05-11 1990-12-06 Canon Inc Recording head control circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59160263U (en) * 1983-04-12 1984-10-26 マックス株式会社 electric printer
JPS60170480A (en) * 1984-02-13 1985-09-03 Fuji Xerox Co Ltd Speed controller for motor
JPH02295749A (en) * 1989-05-11 1990-12-06 Canon Inc Recording head control circuit

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