JPS5733415A - Automatic optimum equalization controlling system - Google Patents
Automatic optimum equalization controlling systemInfo
- Publication number
- JPS5733415A JPS5733415A JP10549580A JP10549580A JPS5733415A JP S5733415 A JPS5733415 A JP S5733415A JP 10549580 A JP10549580 A JP 10549580A JP 10549580 A JP10549580 A JP 10549580A JP S5733415 A JPS5733415 A JP S5733415A
- Authority
- JP
- Japan
- Prior art keywords
- detector
- output
- equalizer
- output waveform
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
- G11B5/027—Analogue recording
- G11B5/035—Equalising
Abstract
PURPOSE:To automatically control an equalizer to the optimum state, by extracting the optimum equalizing state based on the output waveform given from a magnetic recorder/reproducer and then extracting the nonoptimum equalizing state in contrast with the optimum equalizing state. CONSTITUTION:For the output waveform of an equalizer 3, the section of a small level of amplitude corresponds to the section of a large level of amplitude of the output waveform of an integrator 7. Thus the output of the integrator 7 is sliced by the threshold value through a threshold value detector 9. Then whether or not the output waveform of the equalizer 3 passes the zero level at the slicing section is checked by a zero level detector 10 and a rise detector 11. In other words, a switch 14 is controlled by an AND circuit 12 and via a timer 13 to the output of the detector 9 as well as the output of the detector 11. Then the equalizer 3 is controlled by the terminal voltage of a capacitor 6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10549580A JPS5733415A (en) | 1980-07-31 | 1980-07-31 | Automatic optimum equalization controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10549580A JPS5733415A (en) | 1980-07-31 | 1980-07-31 | Automatic optimum equalization controlling system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5733415A true JPS5733415A (en) | 1982-02-23 |
Family
ID=14409173
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10549580A Pending JPS5733415A (en) | 1980-07-31 | 1980-07-31 | Automatic optimum equalization controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5733415A (en) |
-
1980
- 1980-07-31 JP JP10549580A patent/JPS5733415A/en active Pending
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