JPS5728491A - Channel control system - Google Patents
Channel control systemInfo
- Publication number
- JPS5728491A JPS5728491A JP10345380A JP10345380A JPS5728491A JP S5728491 A JPS5728491 A JP S5728491A JP 10345380 A JP10345380 A JP 10345380A JP 10345380 A JP10345380 A JP 10345380A JP S5728491 A JPS5728491 A JP S5728491A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- audio
- signal
- multiplex
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Exchange Systems With Centralized Control (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To increase the usage efficiency of highway, by using a channel memory consisting of separate regions for audio and signal. CONSTITUTION:Incoming and outgoing channel memories SPMF' and SPMB' in a switch module SM' are formed with audio region TSM and signal region NTM, respectively. A multiplex signal from multiplex lines HW-1 and HW-2 is further multiplexed and controlled at a control memory CTLM, and audio and control signals are separately stored at the corresponding location of TSM or NTM channel. The CTLM can indicate whether the channel of the HW-1 and HW-2 is audio or control signal in every channel. Thus, the line corresponding section LM-2' accommodating a PCM line can multiplex 128 lines as they are to all the channels of the HW-2'. As well known, the LM-1' multiplexes subscribers SUB of 120 on the HW-1 with the 8 control channels.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10345380A JPS5728491A (en) | 1980-07-28 | 1980-07-28 | Channel control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10345380A JPS5728491A (en) | 1980-07-28 | 1980-07-28 | Channel control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5728491A true JPS5728491A (en) | 1982-02-16 |
Family
ID=14354439
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10345380A Pending JPS5728491A (en) | 1980-07-28 | 1980-07-28 | Channel control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5728491A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58173998A (en) * | 1982-04-05 | 1983-10-12 | Nec Corp | Controlling system of digital multiplex line signal |
JPS59122098A (en) * | 1982-12-27 | 1984-07-14 | Nec Corp | Digital trunk controller |
-
1980
- 1980-07-28 JP JP10345380A patent/JPS5728491A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58173998A (en) * | 1982-04-05 | 1983-10-12 | Nec Corp | Controlling system of digital multiplex line signal |
JPS59122098A (en) * | 1982-12-27 | 1984-07-14 | Nec Corp | Digital trunk controller |
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