AU594540B2 - Broadband integrated services tdm communication system - Google Patents

Description

r i I ~e 594540

ORICINAL

This document contains the amendments made L;nder Section 49 and is correct for rinting.

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PATENTS ACT 1952-1969 3 0 NOV 1987 COMPTETE SPECIFICATION FOR THE INVENTION ENTITLED

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C V r QC Vc C C I I "BROADBAND INTEGRATED SERVICES TDM COMMUNICA;TION SYSTEM" The following statement is a full description of this invention, including the best method of performing it known to us:- -i '1 fr V 41 t r t r T t t t C t Cr c. t I c

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tst t C t f C Sc This invention relates to a multiplexer/demultiplexer for a digital time-division multiplex communication system for transmitting the digital signals of different services, particularly over a subscriber line, wherein the repetition rate of the frame is 8 kHz.

In the planned broadband communication network, called "broadband ISDN", a problem in the subscriber network is to transmit digital signals for different services of different bandwidth between an exchange and the broadband terminals over the respective subscriber line using time division multiplexing. These are signals from a so-called H4 channel for movingimage transmission at a bit rate of nearly 140 Mb/s, 1920-kb/s signals from so-called HI channels, signals from H2 channels, if present, with approximately 30 Mb/s each; 64-kb/s signals from B channels, and 16-kb/s signals from the D channel, which is the signalling channel. This transmission problem is described, for example, in "NTZ", Vol. 39 (1986), No. 7, PP. 502 to 508, and shown particularly in Fig. 4. The bit rates of the individual H channels have not been standardized yet.

In a known multiplexer/demultiplexer of the aforementioned type a plurality of 1920-kb HI signals are padded to 2176 kb/s and combined with a 136,000-kb/s .14 signal padded to 139,246 kb/s into a 150,144-kb/s TDM signal. Such a multiplex structure suffers from the drawback that the existing bit rates must first be increased to other bit rates before they can be combined by time-division multiplexing. This means that a considerable amount of circuitry in the form of buffers and premultiplexers is required, and that the frame produced contains a considerable proportion of redundant bits.

It is an object of the present invention to provide a multiplexer/demultiplexer which requires a smaller amount of circuitry as a result of its frame structure.

Accordingly, there is provided a multiplexer/demultiplexer for a digital time-division multiplex communication system for transmitting the digr Cr C C C C CC C r C r Cr i CC C C 4 4 Cr C e Cc C CC CU C ts C

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c CC ital signals of different services, particularly over a subscriber line, wherein the repetition rate of the frame is 8 kHz, and wherein tne frame comprises 87 columns and 30 rows which form 2340 8-bit time slots.

The invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 shows the frame structure of the multiplexer/demultiplexer in accordance with the invention, containing one 138, 240-kb/s H4 channel and several 1920-kb/s H12 channels; Fig. 2 is a block diagram of the multiplexer in accordance with the invention; Pig. 3 shows the frame structure of the multiplexer/demultiplexer in accordance with the invention, containing one 138,240-kb/s H4 signal and several 1536-kb/s H11 signals, and Fig. 4 shows the frame structure of the multiplexer/demultiplexer in accordance with the invention, containing several 1920-kb/s H12 signals and four 33,792-kb/s H2 signals.

First, the frame structure of the multiplexer/demultiplexer in accordance with the invention will be explained with the aid of Fig. 1. The smallest unit of the frame is an 8-bit time slot, which is indicated in the left upper corner. Since the frame repetition rate, lk. FS. C CO mentioned above, is 8 kHz, such a time slot has forms a 64-kb/s channel. The frame has 78 columns and 30 rows, 78 x 30 2340 8-bit time slots.

Accordingly, the output bit rate of the multiplexer is 149,760 kb/s. This bit rate has the advantage that it is exactly equal to the bit rate of the 003 hierachy of the American "SONET" system.

The following embodiments will show that the frame described, which describes the basic operation of the multiplexer/demultiplexer in accordance with the invention, can advantageously contain digital signals of particular bit rates as are currently under discussion, the design of the multiplexer being simple in that only very few buffers are required.

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1 i I-~I- In a preferred embodiment, the frame uses 72 columns for transmitting a 138,240-kb/s H4 broadband signal, while the remaining 6 columns, whose capacities are 1920 kb/s each, are used for transmitting several 1920-kb/s H12 narrow-band signals.

Fig. 1 shows that columns 14, 27, 53, and 66 contain H12 signals, which are designated by the letters a to e, while column 1 contains synchronizing signals, two 64-kb/s B signals, and one 16-kb D signal. In addition to the signals given in column 1, further narrow-band digital signals may be transmitted to fully utilize the 1920-kb/s transmission capacity of the channel f formed by column 1. The uniform distribution of o the channels a to f to the 78 columns as shown in Fig. 1 has the advantage that only few buffers are required in the multiplexer and the 0 S demultiplexer, as will become apparent in connection with Fig. 2. With the frame contents shown in Fig. 1, the capacity of the broadband channel S formed by 72 columns is fully utilized for the transmission of the 138,240-kb/s H4 signal. This bit rate is one of the rates currently under discussion for the transmission of the moving-image signal in the sub- S scriber network.

Fig. 2 shows that the multiplexer characterized by the frame described is simple in construction.

To combine several digital signals into the TDM signal f to be transmitted in column 1 of the frame of Fig. 1, the multiplexer of Fig. 2 contains an "ISDN multiplexer" 100. Its inputs are presented with two 64-kb/s B signals, one 16-kb/s D signal, and several signals collectively designated M, such as signals for signalling or testing purposes, including the synchronizing signal from the ISDN channel in which the two B signals and the D signal are transmitted.

In a serial-to-parallel converter 101, the TDM output signal f of the ISDN multiplexer 100, whose bit rate is 1920 kb/s even if only a part thereof consists of intelligence or control signals, is converted into a i r B j i j (3 i i r*amvu i 1o I St.

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t WI at a a ar a, ar SC a sequence of 8-bit words, also called "octet", which is placed on a bus 103 in the proper time slots. As will be explained below, further circuits place digital signals from other channels on this bus 103 in the time slots assigned to these signals, so that the multiplex signal is formed on this bus in the usual manner. The insertion of the various signals into the TDM signal to be formed is controlled by a frame controller 104, to which the 1 49,760-kHz system clock is applied. This frame controller determines the start of the frame with the aid of the ISDN synchronizing signal ("Sync"), which is contained in the TDM output signal f of the ISDN multiplexer 100, and which it takes from this signal s via an input line connected to the serial-to-parallel converter 101.

Besides the input signals for the ISDN multiplexer 100, the pulse frame shown in Fig. 1 contains a 138,240-kb/s H4 signal and five 1920-kb/s HI1 signals a to e. A serial-to-parallel converter 105 converts the H4 signal into an 8-bit word sequence which passes through a buffer 106 and a changeover switch S2 to the bus 103. The five H12 signals a to e are converted by an arrangement 107 of serial-to-parallel converters into 8-bit word sequences which are applied through an arrangement S1 of changeover switches to the bus 103. In this mode, the changeover switches S1 and S2 are in the state in which they pass the signals described and block their other input signals, which have not been explained yet. The frame controller 104 controls the outputs of the serial-to-parallel converter 101, the buffer 106, and the arrangement 107 of serial-to-parallel converters in such a way that in each row of the frame, an 8-bit word from the output signal f of the ISDN multiplexer 100 is placed on the bus 103 in column 1, an 8-bit word from the H4 input signal in each of columns 2 to 13, 15 to 26, 28 to 39, 41 to 52, 54 to 65, and 67 to 78, and an 8-bit word from the five H12 input signals a to e in each of columns 14, 27, 40, 53 and 66.

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t! 1 A' r pr At the bit rates given above, the buffer 106 needs to have a capacity of only a single 8-bit word. No further buffers are necessary to process the signals described so far, for the frame contents shown in Fig. 1.

A parallel-to-serial converter 108 converts the TDM signal carried by the bus 103 into a serial 149,760-kb/s data stream.

If the multiplexer is to be designed for no other input signals than those described so far, the changeover switches Si and S2 as well as those devices in Fig. 2 which have not been described yet and are provided for processing other input signals will be omitted.

S101' If, instead of the five 1920-kb/s H12 signals, five 1536-kb/s H11 signals are to be transmitted, these five input signals, likewise desig- C T 4 Snated a to e in Fig. 2, will be applied through serial-to-parallel converters 109, buffers 110, and the changeover switches Sl to the bus 103, with r t the changeover switches Sl blocking the H12 signals and passing the H.1 signals in this mode. For each of the Hll input signals, the buffers 110 tc need to have a capacity of only a single 8-bit word.

The reason why only so little storage space is needed is as follows.

The ratio of the bit rates of the H12 and H11 signals is exactly 5:4.

SHence, exactly 4/5 of the capacity of a channel formed by one column of the K0 frame must be used for transmitting a 1536-kb/s Hll signal. In other words, four of five time slots of a column are used for the Hll signal, and one remains free or is used otherwise.

In Fig. 3, column 14 contains an Hll signal whose unused time slots are located in every fifth row of the column. It is this configuration which makes it possible to manage with an 8-bit buffer for each Hll signal.

The contents of the other columns intended for the transmission of Hll signals a to e, columns 27, 40, 53, and 66, correspond to those of columns 14 in Fig. 3. The remaining contents of the frame shown in Fig. 3 correspond to those shown in Fig. 1. In connection with Figs. 1 and 3, it should be noted that in the columns intended for H12 and H1l, any other 6 d i' i ii irl i f 11 1 ~Sll"TE4"4 r t e r r c r t e

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signal can be transmitted instead of H12 or Hll. For example, 30 64-kb/s B signals can be transmitted in such a column.

A mixture of H11 and H12 could be readily implemented with suitable circuitry but would be unrealistic because the bit rate for a concrete application is fixed at H12 1920 kb/s or at Hll 1536 kb/s. At the present time it is still open which of these two bit rates will be standardized. It is also possible, of course, to design the multiplexer either only for H12 or only for Hll, in which case the changeover switches S and the devices provided for the unused bit rate are unnecessary.

tio' For applications in which four 33,792-kb/s H2 signals are to be transmitted instead of the H4 signal, a serial-to-parallel converter 111 and a Sbuffer 112 are provided. The serial-to-parallel converter 111 converts the t four serial 33,792-kb/s H12 input signals into a sequence of 8-bit words with a repetition rate of 16,896 words per second. The serial-to-parallel converter is controlled so as to combine the bits of the four H12 input signals i, j, k, and 1 into 8 bit words with the bit pattern ijklijkl, which appear at its output in parallel form.

The buffer 112 needs to have a capacity of only 5 8-bit words and is so controlled by the frame controller 104 as to pass the 8-bit words to the 2p, bus 103 in those time slots of the frame which are hatched in Fig. 4. In this mode for transmitting four H2 signals, the changeover switch S2 is in the position in which it passes the signals from the buffer 112 and blocks those from the buffer 106. It is also possible, of course, to design the multiplexer for only one of these two modes (1 x H4 or 4 x H2).

In Fig. 4, the frame has the same contents as in Figs. 1 and 3 (it being left open whether in columns 14, 27, 40, 53, and 66, HI1 signals [like in Fig. 3] or H12 signals [like in Fig. 1] are transmitted except that each of the columns contains four H2 signals instead of one H4 signal.

The 72 columns vith 30 time slots per column form a channel with a capacity of 138,240 kb/s (which, as shown in Figs. 3 and 1, is fully utilized 4

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for the transmission of the H14 signal), but to transmit the four H2 signals, a capacity of only 135,168 kb/s is needed. Consequently, 48 time slots (containing 8 bits each) remain unused or can be useJ. otherwise In columns 36 to 39 of the frame shown in Fig. 14, these are the time slots in rows 3, 8, 13, 18, 23, and 28, and in columns 75 to 78, these are the time slots in rows 5, 10, 15, 20, 25 and 30. This regular distribution of 12 blocks, consisting of four time slots each, over the entirety of the time slots of the frame has the advantage that, as already mentioned in connection with Fig. 2, the buffer 112 needs to have a capacity of only 8-bit word8.

@8 Alternatively to this distribution, the 148 unused time slots can be 8evenly distributed over the frame, for instance in such a way that the dis- @8 tance between two of the successive unused time slots is equal to 149 or 148 time slots, but in any case in such a way that none of the unused time slots falls into columns 1, 114, 27, 40, 53, and 66.

The first of the unused time slots, for example, lies in row 1, col-

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umns 49, the second in row 2, columns 20, the third in row 2, column 69, the fourth in row 3, column 39, etc. This regular distribution, too, has the advantage of requiring only a small amount of storage in the 2*MultipleIxer and the demultiplexer.

All other time slots of the 72 columns 2 to 13, 15 to 26, 28 to 39, 141 to 52, 514 to 65, and 67 to 78 contain the 8-bit words appearing at the output of the serial-to-parallel converter 111. For the time slots of columns 2, 3, 14, and 5, this is shown in Fig. 14 by the four 8-bit words structured as explained above.

From the foregoing examples of an advantageous organization of the frame of the multiplexer/demultiplexer in accordance with the invention, it is apparent that the frame can be utilized in many ways; in particular, the embodiments explained show that only little storage capacity is needed in the multiplexer. The same advantages apply to the demultiplexer, which is I ~ff I L r i r a exactly identical in design to the multiplexer and, therefore, requires no separate explanation.

ITe frame contents shown in Fig. 4 can be used to transmit not only four H2 signals as explained in the foregoing, but also one H 4 signal if the bit rate of the latter is 135,168 kb/s. This bit rate, too, is currently nder discussion in connection with the H4 signal. In that case, however, the buffer 106 must have a capacity of two 8-bit words, whereas at the bit rate given in Fig. 2, it needs to be able to contain only a single 8-bit word, as mentioned above.

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Claims (4)

1. A multiplexer/demultiplexer for a digital time-division multiplex communication system for transmitting the digital signals of different ser- vices, particularly over a subscriber line, wherein the repetition rate of the frame is 8 kHz, and wherein the frame comprises 78 columns and 30 rows which form 2340 8-bit time slots each row consisting of time slots of a first group of time slots uniformly dispersed between time slots of a sec- ond group of time slots, the total time slots of the second group in a frame having sufficient capacity to support a broadband H4 data rate.

2. A multiplexer/demultiplexer as claimed in claim 1, wherein the sec- S° ond group comptises 72 columns which form a 138,240-kb/s broadband channel, and wherein the first group comprises 6 columns which form 6 1920-kb/s narrow-band channels. 0

3. A multiplexer/demultiplexer as claimed in claim 2, wherein in one of the narrow-band channels, at least one synchronizing signal as well as

64-kb/s B signals and 16-kb/s D signals are transmitted. 4. A multiplexer/demultiplexer as claimed in claim 2, including means for transmitting in the broadband channel either one 138,240-kb/s H4 dig- ital signal or four 33,792-kb/s H2 digital signals. A multiplexer/demultiplexer as claimed in any one of the preceding claims, including means for transmitting in at least one of the narrow-band channels either a 1920-kb/s H12 digital signal or a 1536-kb/s H11 digital signal. 6. A multiplexer/demultiplexer as claimed in claim 2 or 3, wherein in at least one of the narrow-band channels a 1920-kb/s 112 signal is trans- mitted. 7. A multiplexer/demultiplexer as claimed in any one of claims 2 to wherein in at least one of the narrow-band channels, a 1536-kb/s H11 signal is transmitted, with every fifth of the successive time slots of this chan- nel being unused or used to transmit other signals. LL ;i ~~il i i r_ I r r\:i I ;I i; iii i 8. A multiplexer/demultiplexer as claimed in any one of the preceding claims, wherein in the broadband channel, a 138,240-kb/s H4 signal is transmitted. 9. A multiplexer/demultiplexer as claimed in any one of claims 2, 3, 6, and 7, wherein in the broadband channel, one 135,168-kb/s H4 signal or four 33,792-kb/s H2 signals are transmitted, with 12 blocks from four successive time slots each or 48 individual time slots, distributed regu- larly over the time slots of the broadband channel, being unused or used to transmit other signals. A multiplexer/demultiplexer as claimed in claim 2, wherein the six columns are distributed at regular intervals over the 78 columns of the S frame. 4 0 S 11. A multiplexer/demultiplexer as claimed in any one of claims 1 to t including: an ISDN multiplexer arranged to combine two 64 kb/s channels, one 16 kb/s D channel and an ISDN synchronizing onto an 8 bit bus via first serial-to-parallel converter means to convert the broadband H4 data to 8 nr parallel bit format, first buffer store means through which the broadband data in parallel bit format is applied to the 8 bit bus; third serial-to- parallel converter means to convert a first plurality of H11 or H12 chan- nels to a corresponding first plurality of 8 bit parallel signals and frame control meais driven by a clock at the line data rate and the synchronizing signal to control the times at which the outputs of the first serial-to- parallel converter means, the first buffer store, and the third serial-to- parallel converter means are applied to the bus; a parallel-to- al converter means to convert the data on the bus to a line data rate. 12. A multiplexer/demultiplexer as claimed in claim 11 including first changeover switch means between the third serial-to-parallel converter means and the bus, fourth serial-to-parallel converter means to convert a second plurality of Hll or H12 channels to a corresponding second plurality riKi of 8 bit parallel signals, second buffer store means between the fourth i L ,I -~I i r" I serial-to-parallel converter means and the first changeover switch means whereby either the first or the second plurality of Hll or H12 channels are multiplexed onto the bus via the first changeover switch means under the control of the frame control means. 13. A multiplexer/demultiplexer as claimed in claim 11. or claim 12 in- cluding second changeover switch means between the first buffer store means and the bus to which a plurality of H2 channels are applied via fifth serial-to-parallel converter means through fourth buffer store means, whereby either the HA data or the H2 channels are multiplexed onto the bus under the control of the frame control means. 14. A multiplexer/demultiplexer as claimed in any one of the preceding claims wherein the demultiplexer is the mirror image of the multiplexer. 15. A multiplexer/demultiplexer substantially as herein described with reference to 1 1 to 4 of the accompanying drawings. DATED THIS TWENTY-FIRST DAY OF DECEMBER, 1989 ALCATEL N.V. 00 OQ 09 0 o 9 099090 0 0 40 0 O 00D tO 0( I 0 {.2 T i 'I y. 1'I i '.A q:(FII--~ LiZnr -s^