JPS5723869A - Function testing method - Google Patents

Function testing method

Info

Publication number
JPS5723869A
JPS5723869A JP9840080A JP9840080A JPS5723869A JP S5723869 A JPS5723869 A JP S5723869A JP 9840080 A JP9840080 A JP 9840080A JP 9840080 A JP9840080 A JP 9840080A JP S5723869 A JPS5723869 A JP S5723869A
Authority
JP
Japan
Prior art keywords
test
board
conductive
testing method
broadwise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9840080A
Other languages
Japanese (ja)
Inventor
Masaharu Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9840080A priority Critical patent/JPS5723869A/en
Publication of JPS5723869A publication Critical patent/JPS5723869A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To reduce the process mounting components for test, by placing a conductive sheet which is conductive only broadwise between a tested printed board and an accessory to be mounted for the test. CONSTITUTION:A device to be tested 100 mounting a connector 2, various semiconductors 3, and jumper pins 4 and the like on a printed board is prepared with a board 300 for testing. On the board 300, components to be mounted for the test of the device 100 are mounted at a position 5'. In case of test, the test board 300 is braught and it is conductive to the device 100 via a conductive sheet 200 which is conductive only broadwise as shown in figure, and the function test is made as if accessories were mounted on the printed wiring board 1. The alignment of the both are used for alignment guide rails as shown in figure.
JP9840080A 1980-07-18 1980-07-18 Function testing method Pending JPS5723869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9840080A JPS5723869A (en) 1980-07-18 1980-07-18 Function testing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9840080A JPS5723869A (en) 1980-07-18 1980-07-18 Function testing method

Publications (1)

Publication Number Publication Date
JPS5723869A true JPS5723869A (en) 1982-02-08

Family

ID=14218777

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9840080A Pending JPS5723869A (en) 1980-07-18 1980-07-18 Function testing method

Country Status (1)

Country Link
JP (1) JPS5723869A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0232068U (en) * 1988-08-22 1990-02-28
US4926117A (en) * 1988-05-02 1990-05-15 Micron Technology, Inc. Burn-in board having discrete test capability
US5220280A (en) * 1989-05-11 1993-06-15 Vlsi Technology, Inc. Method and an apparatus for testing the assembly of a plurality of electrical components on a substrate
US5856041A (en) * 1995-10-20 1999-01-05 Matsushita Electric Industrial Co., Ltd. Sealed secondary cell
US6027831A (en) * 1996-12-26 2000-02-22 Matsushita Electric Industrial Co., Ltd. Square type enclosed storage battery

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4926117A (en) * 1988-05-02 1990-05-15 Micron Technology, Inc. Burn-in board having discrete test capability
JPH0232068U (en) * 1988-08-22 1990-02-28
US5220280A (en) * 1989-05-11 1993-06-15 Vlsi Technology, Inc. Method and an apparatus for testing the assembly of a plurality of electrical components on a substrate
US5856041A (en) * 1995-10-20 1999-01-05 Matsushita Electric Industrial Co., Ltd. Sealed secondary cell
US6027831A (en) * 1996-12-26 2000-02-22 Matsushita Electric Industrial Co., Ltd. Square type enclosed storage battery

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