JPS57211657A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS57211657A
JPS57211657A JP9505482A JP9505482A JPS57211657A JP S57211657 A JPS57211657 A JP S57211657A JP 9505482 A JP9505482 A JP 9505482A JP 9505482 A JP9505482 A JP 9505482A JP S57211657 A JPS57211657 A JP S57211657A
Authority
JP
Japan
Prior art keywords
data processing
processing system
data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9505482A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0241056B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Dei Deikuson Jierii
Ei Marazasu Jierarudo
Yuu Maakeru Jierarudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS57211657A publication Critical patent/JPS57211657A/ja
Publication of JPH0241056B2 publication Critical patent/JPH0241056B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Transfer Between Computers (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
JP9505482A 1981-06-05 1982-06-04 Data processing system Granted JPS57211657A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/270,951 US4490782A (en) 1981-06-05 1981-06-05 I/O Storage controller cache system with prefetch determined by requested record's position within data block

Publications (2)

Publication Number Publication Date
JPS57211657A true JPS57211657A (en) 1982-12-25
JPH0241056B2 JPH0241056B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-09-14

Family

ID=23033545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9505482A Granted JPS57211657A (en) 1981-06-05 1982-06-04 Data processing system

Country Status (2)

Country Link
US (1) US4490782A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS57211657A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (1)

* Cited by examiner, † Cited by third party
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JPS58155464A (ja) * 1981-11-27 1983-09-16 ストレ−ジ・テクノロジ−・コ−ポレ−シヨン 順次デ−タ・ストリ−ムの検出方法

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US4811280A (en) * 1983-06-16 1989-03-07 American Telephone And Telegraph Company Dual mode disk controller
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US4807110A (en) * 1984-04-06 1989-02-21 International Business Machines Corporation Prefetching system for a cache having a second directory for sequentially accessed blocks
JPS60235269A (ja) * 1984-05-08 1985-11-21 Toshiba Corp デ−タ転送制御装置
US4637024A (en) * 1984-11-02 1987-01-13 International Business Machines Corporation Redundant page identification for a catalogued memory
US4774654A (en) * 1984-12-24 1988-09-27 International Business Machines Corporation Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory
US4875155A (en) * 1985-06-28 1989-10-17 International Business Machines Corporation Peripheral subsystem having read/write cache with record access
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US4821185A (en) * 1986-05-19 1989-04-11 American Telephone And Telegraph Company I/O interface system using plural buffers sized smaller than non-overlapping contiguous computer memory portions dedicated to each buffer
US5136692A (en) * 1987-02-13 1992-08-04 International Business Machines Corporation Memory disk buffer manager
US4972316A (en) * 1987-03-30 1990-11-20 International Business Machines Corporation Method of handling disk sector errors in DASD cache
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US4980823A (en) * 1987-06-22 1990-12-25 International Business Machines Corporation Sequential prefetching with deconfirmation
US4905188A (en) * 1988-02-22 1990-02-27 International Business Machines Corporation Functional cache memory chip architecture for improved cache access
US5016121A (en) * 1988-02-25 1991-05-14 Tandon Corporation Disk drive controller system
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JP2826857B2 (ja) * 1989-12-13 1998-11-18 株式会社日立製作所 キャッシュ制御方法および制御装置
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US5325509A (en) * 1991-03-05 1994-06-28 Zitel Corporation Method of operating a cache memory including determining desirability of cache ahead or cache behind based on a number of available I/O operations
JP3087429B2 (ja) * 1992-04-03 2000-09-11 株式会社日立製作所 記憶装置システム
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US5751990A (en) * 1994-04-26 1998-05-12 International Business Machines Corporation Abridged virtual address cache directory
US5606688A (en) * 1994-08-31 1997-02-25 International Business Machines Corporation Method and apparatus for dynamic cache memory allocation via single-reference residency times
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US5649155A (en) * 1995-03-31 1997-07-15 International Business Machines Corporation Cache memory accessed by continuation requests
JP3865775B2 (ja) 1995-04-11 2007-01-10 キネテック インコーポレイテッド データ処理システムにおけるデータの識別
JP3707854B2 (ja) * 1996-03-01 2005-10-19 株式会社東芝 キャッシュ機能を有するコンピュータ及びキャッシュメモリ制御方法
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US5875454A (en) * 1996-07-24 1999-02-23 International Business Machiness Corporation Compressed data cache storage system
US5845318A (en) * 1996-10-28 1998-12-01 International Business Machines Corporation Dasd I/O caching method and application including replacement policy minimizing data retrieval and storage costs
US6065100A (en) * 1996-11-12 2000-05-16 Micro-Design International Caching apparatus and method for enhancing retrieval of data from an optical storage device
US5895485A (en) * 1997-02-24 1999-04-20 Eccs, Inc. Method and device using a redundant cache for preventing the loss of dirty data
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
JP2002516446A (ja) 1998-05-15 2002-06-04 ストーリッジ テクノロジー コーポレーション サイズ可変データブロックのキャッシュ方法
US6327644B1 (en) 1998-08-18 2001-12-04 International Business Machines Corporation Method and system for managing data in cache
US6381677B1 (en) 1998-08-19 2002-04-30 International Business Machines Corporation Method and system for staging data into cache
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US6842826B1 (en) * 2000-06-07 2005-01-11 International Business Machines Incorporated Method and apparatus for providing efficient management of least recently used (LRU) algorithm insertion points corresponding to defined times-in-cache
US7039766B1 (en) * 2000-10-12 2006-05-02 International Business Machines Corporation Prescheduling sequential data prefetches in a preexisting LRU cache
US7234021B1 (en) * 2001-10-05 2007-06-19 Emc Corporation Methods and apparatus for accessing data elements using improved hashing techniques
US7139879B2 (en) * 2003-07-24 2006-11-21 International Business Machinces Corporation System and method of improving fault-based multi-page pre-fetches
US20050131561A1 (en) * 2003-12-16 2005-06-16 Dell Products L.P. Information handling system including docking station with digital audio capability
US7353146B2 (en) * 2003-12-22 2008-04-01 The Mathworks, Inc. Block processing of input data in graphical programming environments
US8214447B2 (en) * 2004-06-08 2012-07-03 Bose Corporation Managing an audio network
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US8185576B2 (en) 2006-03-14 2012-05-22 Altnet, Inc. Filter for a distributed network
US7934046B2 (en) * 2008-07-02 2011-04-26 International Business Machines Corporation Access table lookup for bus bridge
US9489149B2 (en) * 2014-06-16 2016-11-08 Netapp, Inc. Methods and systems for using a write cache in a storage system
US11416447B2 (en) * 2017-06-08 2022-08-16 Hitachi Vantara Llc Deduplicating distributed erasure coded objects
JP7011156B2 (ja) * 2017-11-20 2022-01-26 富士通株式会社 ストレージ制御装置およびプログラム
CN110879687B (zh) * 2019-10-18 2021-03-16 蚂蚁区块链科技(上海)有限公司 一种基于磁盘存储的数据读取方法、装置及设备

Citations (2)

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JPS55157056A (en) * 1979-05-25 1980-12-06 Nec Corp Disc cash control system

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JPS55157056A (en) * 1979-05-25 1980-12-06 Nec Corp Disc cash control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155464A (ja) * 1981-11-27 1983-09-16 ストレ−ジ・テクノロジ−・コ−ポレ−シヨン 順次デ−タ・ストリ−ムの検出方法

Also Published As

Publication number Publication date
US4490782A (en) 1984-12-25
JPH0241056B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-09-14

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