JPS57203329A - Analog-to-digital converter - Google Patents

Analog-to-digital converter

Info

Publication number
JPS57203329A
JPS57203329A JP8749781A JP8749781A JPS57203329A JP S57203329 A JPS57203329 A JP S57203329A JP 8749781 A JP8749781 A JP 8749781A JP 8749781 A JP8749781 A JP 8749781A JP S57203329 A JPS57203329 A JP S57203329A
Authority
JP
Japan
Prior art keywords
converter
output
data
adder
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8749781A
Other languages
Japanese (ja)
Inventor
Masao Shiozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8749781A priority Critical patent/JPS57203329A/en
Publication of JPS57203329A publication Critical patent/JPS57203329A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters

Abstract

PURPOSE:To simplify the constitution of an A/D converter and to process an input having a high changing speed in a short time to deliver correct data, by using an adder and a register in place of a counter of a parallel comparison type A/D converter. CONSTITUTION:An analog input signal A is fed to a subtractor 15, and an output signal B obtained by subtracting the output value of a D/A converter 14 is supplied to an A/D converter 11. The output of the converter 11 is added with the data of a register 13 which holds the output of an adder 12 through the adder 12. The timing with which the output data of the adder 12 is set to the register 13 is indicated by a timing signal 16. Then the signal output held at the register 13 is converted into an analog signal through the converter 14 to be applied to the subtractor 15. The A/D converter of such constitution does not deliver conversion data 17 for an initial certain period of time and then delivers the data 17 after the converting action follows the analog input. Thus an input having a high changing speed is processed in a short time, and the correct data 17 is delivered.
JP8749781A 1981-06-09 1981-06-09 Analog-to-digital converter Pending JPS57203329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8749781A JPS57203329A (en) 1981-06-09 1981-06-09 Analog-to-digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8749781A JPS57203329A (en) 1981-06-09 1981-06-09 Analog-to-digital converter

Publications (1)

Publication Number Publication Date
JPS57203329A true JPS57203329A (en) 1982-12-13

Family

ID=13916600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8749781A Pending JPS57203329A (en) 1981-06-09 1981-06-09 Analog-to-digital converter

Country Status (1)

Country Link
JP (1) JPS57203329A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224332A (en) * 1984-03-23 1985-11-08 テクトロニツクス・インコーポレイテツド Sampling device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224332A (en) * 1984-03-23 1985-11-08 テクトロニツクス・インコーポレイテツド Sampling device
JPH0219653B2 (en) * 1984-03-23 1990-05-02 Tektronix Inc

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