JPS57201352A - Balance-unbalance conversion circuit - Google Patents

Balance-unbalance conversion circuit

Info

Publication number
JPS57201352A
JPS57201352A JP8493681A JP8493681A JPS57201352A JP S57201352 A JPS57201352 A JP S57201352A JP 8493681 A JP8493681 A JP 8493681A JP 8493681 A JP8493681 A JP 8493681A JP S57201352 A JPS57201352 A JP S57201352A
Authority
JP
Japan
Prior art keywords
amplifier circuit
differential amplifier
burst signal
digital telephone
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8493681A
Other languages
Japanese (ja)
Inventor
Naoki Matsuo
Fujio Amamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP8493681A priority Critical patent/JPS57201352A/en
Publication of JPS57201352A publication Critical patent/JPS57201352A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00Arrangements affording multiple use of the transmission path
    • H04L5/14Two-way operation using the same type of signal, i.e. duplex
    • H04L5/1469Two-way operation using the same type of signal, i.e. duplex using time-sharing
    • H04L5/1484Two-way operation using the same type of signal, i.e. duplex using time-sharing operating bytewise
    • H04L5/1492Two-way operation using the same type of signal, i.e. duplex using time-sharing operating bytewise with time compression, e.g. operating according to the ping-pong technique

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Bidirectional Digital Transmission (AREA)

Abstract

PURPOSE:To make a transformer unnecessary and to facilitate conversion to LSI in a digital telephone circuit by performing balance-unbalance conversion using electronic switches, a differential amplifier circuit and an inversion amplifier circuit. CONSTITUTION:When receiving, electronic switches 31, 32 are connected to (a) side terminal with the control pulse 54 sent from a digital telephone circuit 9 as a trigger. An outgoing burst signal 50 of an exchange arrives at line terminals 1, 2 of a digital telephone set as a receiving burst signal 51 through a subscriber's line. The receiving burst signal is sent to a differential amplifier circuit consisting of resistances 33-36 and an operational amplifier 41 through d.c. removing condensers 5, 6 and (a) side terminals of switches 31, 32. If the differential amplifier circuit is composed of the operational amplifier 41 which has resistance small in deviation and excellent in temperature characteristic and also has a sufficiently large in-phase component eliminating ratio through a broad band and a broad dynamic range, a voltage caused by induction noise is canceled in the differential amplifier circuit and does not come out to the terminal 44.
JP8493681A 1981-06-04 1981-06-04 Balance-unbalance conversion circuit Pending JPS57201352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8493681A JPS57201352A (en) 1981-06-04 1981-06-04 Balance-unbalance conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8493681A JPS57201352A (en) 1981-06-04 1981-06-04 Balance-unbalance conversion circuit

Publications (1)

Publication Number Publication Date
JPS57201352A true JPS57201352A (en) 1982-12-09

Family

ID=13844547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8493681A Pending JPS57201352A (en) 1981-06-04 1981-06-04 Balance-unbalance conversion circuit

Country Status (1)

Country Link
JP (1) JPS57201352A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5275904A (en) * 1975-12-22 1977-06-25 Nippon Telegr & Teleph Corp <Ntt> Semi-double circuit
JPS5276813A (en) * 1975-12-22 1977-06-28 Nippon Telegr & Teleph Corp <Ntt> Balanced signal extractions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5275904A (en) * 1975-12-22 1977-06-25 Nippon Telegr & Teleph Corp <Ntt> Semi-double circuit
JPS5276813A (en) * 1975-12-22 1977-06-28 Nippon Telegr & Teleph Corp <Ntt> Balanced signal extractions

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