JPS57195830U - - Google Patents

Info

Publication number
JPS57195830U
JPS57195830U JP8246981U JP8246981U JPS57195830U JP S57195830 U JPS57195830 U JP S57195830U JP 8246981 U JP8246981 U JP 8246981U JP 8246981 U JP8246981 U JP 8246981U JP S57195830 U JPS57195830 U JP S57195830U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8246981U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8246981U priority Critical patent/JPS57195830U/ja
Publication of JPS57195830U publication Critical patent/JPS57195830U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP8246981U 1981-06-04 1981-06-04 Pending JPS57195830U (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8246981U JPS57195830U (enExample) 1981-06-04 1981-06-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8246981U JPS57195830U (enExample) 1981-06-04 1981-06-04

Publications (1)

Publication Number Publication Date
JPS57195830U true JPS57195830U (enExample) 1982-12-11

Family

ID=29877932

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8246981U Pending JPS57195830U (enExample) 1981-06-04 1981-06-04

Country Status (1)

Country Link
JP (1) JPS57195830U (enExample)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5364470A (en) * 1976-11-19 1978-06-08 Mitsubishi Electric Corp Lead frame of semiconductor device
JPS5571030A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Mounting system for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5364470A (en) * 1976-11-19 1978-06-08 Mitsubishi Electric Corp Lead frame of semiconductor device
JPS5571030A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Mounting system for semiconductor device

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