JPS57188166A - System for locking phase of clock signal aginst data flow modulated by frequency on carrier - Google Patents

System for locking phase of clock signal aginst data flow modulated by frequency on carrier

Info

Publication number
JPS57188166A
JPS57188166A JP57072511A JP7251182A JPS57188166A JP S57188166 A JPS57188166 A JP S57188166A JP 57072511 A JP57072511 A JP 57072511A JP 7251182 A JP7251182 A JP 7251182A JP S57188166 A JPS57188166 A JP S57188166A
Authority
JP
Japan
Prior art keywords
aginst
carrier
frequency
clock signal
data flow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57072511A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0452551B2 (enExample
Inventor
Daburiyu Fueringaa Mitsuchieru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MONORISHITSUKU SYSTEMS CORP
Original Assignee
MONORISHITSUKU SYSTEMS CORP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MONORISHITSUKU SYSTEMS CORP filed Critical MONORISHITSUKU SYSTEMS CORP
Publication of JPS57188166A publication Critical patent/JPS57188166A/ja
Publication of JPH0452551B2 publication Critical patent/JPH0452551B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H03L7/0993—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dc Digital Transmission (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
JP57072511A 1981-04-30 1982-04-28 System for locking phase of clock signal aginst data flow modulated by frequency on carrier Granted JPS57188166A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/259,020 US4424497A (en) 1981-04-30 1981-04-30 System for phase locking clock signals to a frequency encoded data stream

Publications (2)

Publication Number Publication Date
JPS57188166A true JPS57188166A (en) 1982-11-19
JPH0452551B2 JPH0452551B2 (enExample) 1992-08-24

Family

ID=22983167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57072511A Granted JPS57188166A (en) 1981-04-30 1982-04-28 System for locking phase of clock signal aginst data flow modulated by frequency on carrier

Country Status (3)

Country Link
US (1) US4424497A (enExample)
JP (1) JPS57188166A (enExample)
GB (1) GB2099246A (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4498103A (en) * 1982-09-13 1985-02-05 Rca Corporation Slow genlock circuit
US4534036A (en) * 1982-12-08 1985-08-06 Paradyne Corporation Phase tracking loop impairment monitor for modems
GB2132042B (en) * 1982-12-15 1986-09-24 British Broadcasting Corp Frequency and timing sources
EP0134374B1 (fr) * 1983-09-07 1987-12-02 International Business Machines Corporation Horloge à verrouillage de phase
IT1212796B (it) * 1983-12-12 1989-11-30 Ates Componenti Elettron Sincronizzatore di fase di tipo digitale per segnali isofrequenziali, particolarmente per demodulatore di segnali.
EP0157053A3 (en) * 1984-03-19 1987-09-02 Western Digital Corporation High order digital phase lock loop system
US4628461A (en) * 1984-04-30 1986-12-09 Advanced Micro Devices, Inc. Phase detector
US4808884A (en) * 1985-12-02 1989-02-28 Western Digital Corporation High order digital phase-locked loop system
JP2581074B2 (ja) * 1987-05-20 1997-02-12 ソニー株式会社 デジタルｐｌｌ回路
US4841257A (en) * 1988-03-28 1989-06-20 Unisys Corporation High-speed sampling phase detector for clock and data recovery system
US5815041A (en) * 1996-04-12 1998-09-29 Silicon Image, Inc. High-speed and high-precision phase locked loop having phase detector with dynamic logic structure
US6326826B1 (en) 1999-05-27 2001-12-04 Silicon Image, Inc. Wide frequency-range delay-locked loop circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50105364A (enExample) * 1974-01-28 1975-08-20

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3624511A (en) 1969-08-07 1971-11-30 Communications Satellite Corp Nonlinear phase-lock loop
US4017806A (en) 1976-01-26 1977-04-12 Sperry Rand Corporation Phase locked oscillator
US4030045A (en) 1976-07-06 1977-06-14 International Telephone And Telegraph Corporation Digital double differential phase-locked loop

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50105364A (enExample) * 1974-01-28 1975-08-20

Also Published As

Publication number Publication date
GB2099246A (en) 1982-12-01
US4424497A (en) 1984-01-03
JPH0452551B2 (enExample) 1992-08-24

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