JPS57186893A - Time division channel - Google Patents

Time division channel

Info

Publication number
JPS57186893A
JPS57186893A JP7163681A JP7163681A JPS57186893A JP S57186893 A JPS57186893 A JP S57186893A JP 7163681 A JP7163681 A JP 7163681A JP 7163681 A JP7163681 A JP 7163681A JP S57186893 A JPS57186893 A JP S57186893A
Authority
JP
Japan
Prior art keywords
multiplexing degree
channel
multiplexing
output
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7163681A
Other languages
Japanese (ja)
Inventor
Yoshinori Yoshida
Masakatsu Kuroki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7163681A priority Critical patent/JPS57186893A/en
Publication of JPS57186893A publication Critical patent/JPS57186893A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To independently execute switching control in a time switch, by providing 2 channel memories in the up and down directions, respectively, and connecting each multiplexing channel portion of each time switch. CONSTITUTION:As for channel memories BFMF1, BFMF2 having input multiplexing degree J and output multiplexing degree J, a digital service signal of input multiplexing degree J is inputted to both of them, and a signal of multiplexing degree J controlled by a switch control memory CTLMF is outputted. Also, in the down-direction, channel memories BFMB1, BFMB2 having input multiplexing degree J and output multiplexing degree J are provided, an output signal of multiplexing degree J of the memory BFMF2 is led to the input side of the memory BFMB1, an output controlled by the switch control memory CTLMB becomes common in the memories BFMB1, BFMB2, and becomes a channel signal having multiplexing degree J. Accordingly, the switching control can be executed independently from other switch module.
JP7163681A 1981-05-13 1981-05-13 Time division channel Pending JPS57186893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7163681A JPS57186893A (en) 1981-05-13 1981-05-13 Time division channel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7163681A JPS57186893A (en) 1981-05-13 1981-05-13 Time division channel

Publications (1)

Publication Number Publication Date
JPS57186893A true JPS57186893A (en) 1982-11-17

Family

ID=13466328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7163681A Pending JPS57186893A (en) 1981-05-13 1981-05-13 Time division channel

Country Status (1)

Country Link
JP (1) JPS57186893A (en)

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