JPS57186299A - Data processing device - Google Patents
Data processing deviceInfo
- Publication number
- JPS57186299A JPS57186299A JP56071615A JP7161581A JPS57186299A JP S57186299 A JPS57186299 A JP S57186299A JP 56071615 A JP56071615 A JP 56071615A JP 7161581 A JP7161581 A JP 7161581A JP S57186299 A JPS57186299 A JP S57186299A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- reading
- writing operations
- processing device
- artificial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To perform highly reliable reading and writing operations which are necessary for testing and diagnostic, by installing an aritifical memory having a small capacity which has a processing device with the interface specifications which is smaller to that of an ordinary memory and which is able to perform reading and writing operations, commonly to the interface line. CONSTITUTION:The titled device consists of an aritifical memory 1 which commonly uses an interface line of a processing device P of a memory M and performs reading and writing operations based on the signal on the interface line, an instruction decoding circuit 2 which designates reading and writing operations to the artificial memory 1, a designation flip flop 3 which is set by the command from the processing device P, a memory access managing circuit 4 which generates an access request signal to the artificial memory 1, and a read-out data switching circuit 6 which switches each reading out bus. The artificial memory 1 performs reading and writing operations from the memory M based on the command from the flip flop 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56071615A JPS57186299A (en) | 1981-05-13 | 1981-05-13 | Data processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56071615A JPS57186299A (en) | 1981-05-13 | 1981-05-13 | Data processing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57186299A true JPS57186299A (en) | 1982-11-16 |
JPS6138509B2 JPS6138509B2 (en) | 1986-08-29 |
Family
ID=13465723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56071615A Granted JPS57186299A (en) | 1981-05-13 | 1981-05-13 | Data processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57186299A (en) |
-
1981
- 1981-05-13 JP JP56071615A patent/JPS57186299A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6138509B2 (en) | 1986-08-29 |
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