JPS57178229A - Camera control system - Google Patents
Camera control systemInfo
- Publication number
- JPS57178229A JPS57178229A JP6243481A JP6243481A JPS57178229A JP S57178229 A JPS57178229 A JP S57178229A JP 6243481 A JP6243481 A JP 6243481A JP 6243481 A JP6243481 A JP 6243481A JP S57178229 A JPS57178229 A JP S57178229A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- supplied
- control system
- ram
- camera control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B7/00—Control of exposure by setting shutters, diaphragms or filters, separately or conjointly
- G03B7/08—Control effected solely on the basis of the response, to the intensity of the light received by the camera, of a built-in light-sensitive device
- G03B7/091—Digital circuits
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure Control For Cameras (AREA)
- Cameras In General (AREA)
- Control By Computers (AREA)
Abstract
PURPOSE:To secure the instantaneous responsiveness for a camera control system using a microprocessor, by using an interruption control program to fetch an input data into an RAM. CONSTITUTION:The system clock CP is supplied to a microprocessor MPU from an oscillating circuit OSC, and at the same time the interruption signal produced from the clock CP by a timer TM is supplied to the MPU with every constant period. The MPU executes a main program in the period during which no interruption signal is supplied and executes an interruption control program in the period during which the interruption signal is supplied to replace the data of an RAM to the latest one. In such way, the contents of the RAM is replaced sequentially based on an interruption program to secure the instantaneous responsiveness which is required for a camera control system.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6243481A JPS57178229A (en) | 1981-04-27 | 1981-04-27 | Camera control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6243481A JPS57178229A (en) | 1981-04-27 | 1981-04-27 | Camera control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57178229A true JPS57178229A (en) | 1982-11-02 |
Family
ID=13200069
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6243481A Pending JPS57178229A (en) | 1981-04-27 | 1981-04-27 | Camera control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57178229A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS516537A (en) * | 1974-07-05 | 1976-01-20 | Canon Kk | ROSHUTSUSEIGYOHOHO |
-
1981
- 1981-04-27 JP JP6243481A patent/JPS57178229A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS516537A (en) * | 1974-07-05 | 1976-01-20 | Canon Kk | ROSHUTSUSEIGYOHOHO |
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