JPS57168168A - Level detection circuit - Google Patents

Level detection circuit

Info

Publication number
JPS57168168A
JPS57168168A JP56053110A JP5311081A JPS57168168A JP S57168168 A JPS57168168 A JP S57168168A JP 56053110 A JP56053110 A JP 56053110A JP 5311081 A JP5311081 A JP 5311081A JP S57168168 A JPS57168168 A JP S57168168A
Authority
JP
Japan
Prior art keywords
output
multiplier
sine wave
given
level detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56053110A
Other languages
Japanese (ja)
Inventor
Yutaka Ishikawa
Kenji Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56053110A priority Critical patent/JPS57168168A/en
Publication of JPS57168168A publication Critical patent/JPS57168168A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To simplify the scale of a hardware by a level detection in which an input sine wave Acosomega1T is converted to Asinomega1T by operation in a sine wave level of a sample system such as a time-sharing multiplex communication system or the like and a square sum is taken between the two values. CONSTITUTION:A sine wave Acosomega1T is input into an terminal 8 and multiplied by a first specific value sinalpha from 16 with a first multiplier 1. Acosomega1Tsinalpha is produced at the output 9. On the other hand, (Asinomega1T+2) is given to the output 10 of a delay circuit 2 adapted to delay said sine wave Acosomega1T by a given time. The output of the multiplier 1 is subtracted 3 with respect to the output of the delay circuit 2 and the formulaIis provided to the output 11. This value is multi- plied by a second specific 1/cosalpha from 17 with a multiplier 4 and the formula II is given to 12. Then, the output (Asinomega1T)<2> of a multiplier 5 is added 7 to the output (Acosomega1T)<2> of a multiplier 6. This eliminates any filter thereby simplifying the circuit.
JP56053110A 1981-04-10 1981-04-10 Level detection circuit Pending JPS57168168A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56053110A JPS57168168A (en) 1981-04-10 1981-04-10 Level detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56053110A JPS57168168A (en) 1981-04-10 1981-04-10 Level detection circuit

Publications (1)

Publication Number Publication Date
JPS57168168A true JPS57168168A (en) 1982-10-16

Family

ID=12933652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56053110A Pending JPS57168168A (en) 1981-04-10 1981-04-10 Level detection circuit

Country Status (1)

Country Link
JP (1) JPS57168168A (en)

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