JPS57163759U - - Google Patents

Info

Publication number
JPS57163759U
JPS57163759U JP5024781U JP5024781U JPS57163759U JP S57163759 U JPS57163759 U JP S57163759U JP 5024781 U JP5024781 U JP 5024781U JP 5024781 U JP5024781 U JP 5024781U JP S57163759 U JPS57163759 U JP S57163759U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5024781U
Other languages
Japanese (ja)
Other versions
JPS629755Y2 (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1981050247U priority Critical patent/JPS629755Y2/ja
Publication of JPS57163759U publication Critical patent/JPS57163759U/ja
Application granted granted Critical
Publication of JPS629755Y2 publication Critical patent/JPS629755Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP1981050247U 1981-04-09 1981-04-09 Expired JPS629755Y2 (en:Method)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981050247U JPS629755Y2 (en:Method) 1981-04-09 1981-04-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981050247U JPS629755Y2 (en:Method) 1981-04-09 1981-04-09

Publications (2)

Publication Number Publication Date
JPS57163759U true JPS57163759U (en:Method) 1982-10-15
JPS629755Y2 JPS629755Y2 (en:Method) 1987-03-06

Family

ID=29846964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981050247U Expired JPS629755Y2 (en:Method) 1981-04-09 1981-04-09

Country Status (1)

Country Link
JP (1) JPS629755Y2 (en:Method)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123617A (ja) * 2005-10-28 2007-05-17 Toshiba Corp プリント配線板、プリント配線板を内蔵する電子機器、及びプリント配線板の製造方法
JPWO2021235196A1 (en:Method) * 2020-05-21 2021-11-25

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6476871B2 (ja) * 2014-05-22 2019-03-06 株式会社村田製作所 回路基板、蓄電装置、電池パックおよび電子機器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5315049U (en:Method) * 1976-07-20 1978-02-08
JPS5680196A (en) * 1979-12-05 1981-07-01 Hitachi Ltd Method of forming electrode for printed circuit board
JPS56117570U (en:Method) * 1980-02-12 1981-09-08

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5315049U (en:Method) * 1976-07-20 1978-02-08
JPS5680196A (en) * 1979-12-05 1981-07-01 Hitachi Ltd Method of forming electrode for printed circuit board
JPS56117570U (en:Method) * 1980-02-12 1981-09-08

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123617A (ja) * 2005-10-28 2007-05-17 Toshiba Corp プリント配線板、プリント配線板を内蔵する電子機器、及びプリント配線板の製造方法
JPWO2021235196A1 (en:Method) * 2020-05-21 2021-11-25
WO2021235196A1 (ja) * 2020-05-21 2021-11-25 パナソニックIpマネジメント株式会社 チップ部品の実装構造
CN115553074A (zh) * 2020-05-21 2022-12-30 松下知识产权经营株式会社 芯片部件的安装构造

Also Published As

Publication number Publication date
JPS629755Y2 (en:Method) 1987-03-06

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