JPS57162589A - Optical junctor system - Google Patents

Optical junctor system

Info

Publication number
JPS57162589A
JPS57162589A JP4739281A JP4739281A JPS57162589A JP S57162589 A JPS57162589 A JP S57162589A JP 4739281 A JP4739281 A JP 4739281A JP 4739281 A JP4739281 A JP 4739281A JP S57162589 A JPS57162589 A JP S57162589A
Authority
JP
Japan
Prior art keywords
junctor
electric wire
optical
circuit
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4739281A
Other languages
Japanese (ja)
Inventor
Hatsuo Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4739281A priority Critical patent/JPS57162589A/en
Publication of JPS57162589A publication Critical patent/JPS57162589A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/52Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements
    • H04Q3/526Optical switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To set the length of an elastic memory for the frame synchronizing purpose similar in the case of application of the electric wire, by forming a junctor having a length with which the use of an electric wire is impossible with an optical fiber to cause a delay equivalent to one frame. CONSTITUTION:An optical junctor using an optical fiber is constituted with an optical transmitting circuit 1, an optical fiber 2, an optical receiving circuit 3 and a delay circuit 4. While a junctor using an electric wire is constituted with a transmitting circuit 5, an electric wire 6 and a receiveing circuit 7 respectively. The delay time of the circuit 4 is set so that the delay time from an input terminal 10 to an output terminal 41 of the optical junctor is equal to the value obtained by adding the delay time equivalent to one frame to the delay time from an input terminal 10 to an output terminal 71 of the junctor using the electric wire. Thus the length of an elastic memory (not shown in the diagram) for frame synchronization and connected to both junctors can be reduced like a junctor circuit using only the electric wire.
JP4739281A 1981-03-31 1981-03-31 Optical junctor system Pending JPS57162589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4739281A JPS57162589A (en) 1981-03-31 1981-03-31 Optical junctor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4739281A JPS57162589A (en) 1981-03-31 1981-03-31 Optical junctor system

Publications (1)

Publication Number Publication Date
JPS57162589A true JPS57162589A (en) 1982-10-06

Family

ID=12773833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4739281A Pending JPS57162589A (en) 1981-03-31 1981-03-31 Optical junctor system

Country Status (1)

Country Link
JP (1) JPS57162589A (en)

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