JPS57157549A - Container for integrated circuit - Google Patents

Container for integrated circuit

Info

Publication number
JPS57157549A
JPS57157549A JP4295681A JP4295681A JPS57157549A JP S57157549 A JPS57157549 A JP S57157549A JP 4295681 A JP4295681 A JP 4295681A JP 4295681 A JP4295681 A JP 4295681A JP S57157549 A JPS57157549 A JP S57157549A
Authority
JP
Japan
Prior art keywords
container
power source
terminal
materials
reinforcing plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4295681A
Other languages
Japanese (ja)
Inventor
Kiyoo Onodera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4295681A priority Critical patent/JPS57157549A/en
Publication of JPS57157549A publication Critical patent/JPS57157549A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To provide a counter-measure for a power source noise at an IC element itself in a container which seals the element by integrally forming a laminate sandwiched between thin ceramic materials between a plurality of conductive materials on the bottom of the container disposed between the power source and a ground terminal. CONSTITUTION:When a printed board 1 mounted with an IC element 2 having a power source terminal 2a and a ground terminal 2b and a capacitor 3 is contained in a container, the container is constructed as below. a lower insulation reinforcing plate 11 is provided on the lowermost of the bottom, the second conductive material 9 having a connecting terminal 9a is placed on the plate 11, and the first conductive material 8 having a connecting terminal 8a is laminated on the material 9 at both sides of a high dielectric material 10. Subsequently, a metallized substrate formed with a power source pattern 7a and a ground pattern 7b is placed on the material 8, and the substrate is covered with an upper insulation reinforcing plate 6. Thereafter, the patterns 7a, 7b are respectively connected to the materials 8, 9. In this manner, the part of eliminating the power source noise is formed simultaneously upon lamination of the container.
JP4295681A 1981-03-24 1981-03-24 Container for integrated circuit Pending JPS57157549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4295681A JPS57157549A (en) 1981-03-24 1981-03-24 Container for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4295681A JPS57157549A (en) 1981-03-24 1981-03-24 Container for integrated circuit

Publications (1)

Publication Number Publication Date
JPS57157549A true JPS57157549A (en) 1982-09-29

Family

ID=12650471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4295681A Pending JPS57157549A (en) 1981-03-24 1981-03-24 Container for integrated circuit

Country Status (1)

Country Link
JP (1) JPS57157549A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59143355A (en) * 1983-02-04 1984-08-16 Nec Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59143355A (en) * 1983-02-04 1984-08-16 Nec Corp Semiconductor integrated circuit device

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