JPS57157366A - Inter-processor communication system - Google Patents

Inter-processor communication system

Info

Publication number
JPS57157366A
JPS57157366A JP56041706A JP4170681A JPS57157366A JP S57157366 A JPS57157366 A JP S57157366A JP 56041706 A JP56041706 A JP 56041706A JP 4170681 A JP4170681 A JP 4170681A JP S57157366 A JPS57157366 A JP S57157366A
Authority
JP
Japan
Prior art keywords
processor
write
information
read
prescribed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56041706A
Other languages
Japanese (ja)
Other versions
JPS6326422B2 (en
Inventor
Isao Shinpo
Yoshiharu Ohira
Hiroshi Utaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56041706A priority Critical patent/JPS57157366A/en
Publication of JPS57157366A publication Critical patent/JPS57157366A/en
Publication of JPS6326422B2 publication Critical patent/JPS6326422B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Abstract

PURPOSE:To elevate reliability of a system, by quickly communicating prescribed information to each processor by means of hardware without executing the software processing or without making it pass through an inter-processor communicating device, in a multiprocessor system. CONSTITUTION:When executing an urgent communication, for instance, a processor 10-1 sends out a write display signal to a write display line, and sets a desired urgent information to a register device 30. In this case, the write display signal of the write display line is led into a write and read-out blocking circuit so that write and read-out are not executed from other processor, and write and read-out gates corresponding to other processor are closed. The information is recorded in a prescribed bit position in the register device 30. Subsequently, each processor executes, for instance, a read-out operation of contents set in the information of the register device 30 periodically by different phase and a prescribed period. In this way, the processor 10-1 is capable of knowing whether urgent information exists or not, and also its contents, and is capable of executing its prescribed operation in accordance with the urgent information.
JP56041706A 1981-03-24 1981-03-24 Inter-processor communication system Granted JPS57157366A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56041706A JPS57157366A (en) 1981-03-24 1981-03-24 Inter-processor communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56041706A JPS57157366A (en) 1981-03-24 1981-03-24 Inter-processor communication system

Publications (2)

Publication Number Publication Date
JPS57157366A true JPS57157366A (en) 1982-09-28
JPS6326422B2 JPS6326422B2 (en) 1988-05-30

Family

ID=12615863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56041706A Granted JPS57157366A (en) 1981-03-24 1981-03-24 Inter-processor communication system

Country Status (1)

Country Link
JP (1) JPS57157366A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49114845A (en) * 1973-02-28 1974-11-01
JPS5285443A (en) * 1976-01-10 1977-07-15 Nec Corp Shut-off system of emergency action circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49114845A (en) * 1973-02-28 1974-11-01
JPS5285443A (en) * 1976-01-10 1977-07-15 Nec Corp Shut-off system of emergency action circuit

Also Published As

Publication number Publication date
JPS6326422B2 (en) 1988-05-30

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