JPS57155853A - Pcm terminal device of building block system - Google Patents

Pcm terminal device of building block system

Info

Publication number
JPS57155853A
JPS57155853A JP4060481A JP4060481A JPS57155853A JP S57155853 A JPS57155853 A JP S57155853A JP 4060481 A JP4060481 A JP 4060481A JP 4060481 A JP4060481 A JP 4060481A JP S57155853 A JPS57155853 A JP S57155853A
Authority
JP
Japan
Prior art keywords
channel
pulse
transmitted
wired
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4060481A
Other languages
English (en)
Inventor
Kazuhisa Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4060481A priority Critical patent/JPS57155853A/ja
Publication of JPS57155853A publication Critical patent/JPS57155853A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
    • H04L5/24—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters
    • H04L5/245—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters with a number of discharge tubes or semiconductor elements which successively connect the different channels to the transmission channels

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Time-Division Multiplex Systems (AREA)
JP4060481A 1981-03-21 1981-03-21 Pcm terminal device of building block system Pending JPS57155853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4060481A JPS57155853A (en) 1981-03-21 1981-03-21 Pcm terminal device of building block system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4060481A JPS57155853A (en) 1981-03-21 1981-03-21 Pcm terminal device of building block system

Publications (1)

Publication Number Publication Date
JPS57155853A true JPS57155853A (en) 1982-09-27

Family

ID=12585112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4060481A Pending JPS57155853A (en) 1981-03-21 1981-03-21 Pcm terminal device of building block system

Country Status (1)

Country Link
JP (1) JPS57155853A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04373227A (ja) * 1991-06-21 1992-12-25 Victor Co Of Japan Ltd 時分割多重化装置
JPH05130086A (ja) * 1991-03-12 1993-05-25 Hitachi Ltd 多重化装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05130086A (ja) * 1991-03-12 1993-05-25 Hitachi Ltd 多重化装置
JPH04373227A (ja) * 1991-06-21 1992-12-25 Victor Co Of Japan Ltd 時分割多重化装置

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