JPS57147334A - Counter circuit - Google Patents

Counter circuit

Info

Publication number
JPS57147334A
JPS57147334A JP3169781A JP3169781A JPS57147334A JP S57147334 A JPS57147334 A JP S57147334A JP 3169781 A JP3169781 A JP 3169781A JP 3169781 A JP3169781 A JP 3169781A JP S57147334 A JPS57147334 A JP S57147334A
Authority
JP
Japan
Prior art keywords
capacitor
charging
waveform shaping
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3169781A
Other languages
Japanese (ja)
Inventor
Kazuhiko Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3169781A priority Critical patent/JPS57147334A/en
Publication of JPS57147334A publication Critical patent/JPS57147334A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K25/00—Pulse counters with step-by-step integration and static storage; Analogous frequency dividers
    • H03K25/02—Pulse counters with step-by-step integration and static storage; Analogous frequency dividers comprising charge storage, e.g. capacitor without polarisation hysteresis

Abstract

PURPOSE:To decrease the number of elements used for a counter circuit by charging a capacitor every time an input pulse is applied, and then discharging the capacitor when a charging voltage exceeds the threshold level of a waveform shaping circuit. CONSTITUTION:Transistors (TR) E1 and E2 are connected in series between power terminals, and a capacitor C1 is connected between a connection point between those two TRs and a reference potential terminal, constituting a charging and discharging circuit. An input pulse is applied to the gate of the TRE1, whose output is applied to a waveform shaping circuit; and the output of the waveform shaping circuit is applied to the gate of the TRE2. Every time the input pulse is applied, the TRE1 turns on and the charging voltage of the capacitor C1 rises stepwise. When the output voltage of the charging and discharging circuit exceeds the threshold level of the waveform shaping circuit, the TRE2 turns on by its output to discharge the charge of the capacitor C1.
JP3169781A 1981-03-05 1981-03-05 Counter circuit Pending JPS57147334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3169781A JPS57147334A (en) 1981-03-05 1981-03-05 Counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3169781A JPS57147334A (en) 1981-03-05 1981-03-05 Counter circuit

Publications (1)

Publication Number Publication Date
JPS57147334A true JPS57147334A (en) 1982-09-11

Family

ID=12338259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3169781A Pending JPS57147334A (en) 1981-03-05 1981-03-05 Counter circuit

Country Status (1)

Country Link
JP (1) JPS57147334A (en)

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