JPS57135492A - Control system for store buffer - Google Patents

Control system for store buffer

Info

Publication number
JPS57135492A
JPS57135492A JP56019589A JP1958981A JPS57135492A JP S57135492 A JPS57135492 A JP S57135492A JP 56019589 A JP56019589 A JP 56019589A JP 1958981 A JP1958981 A JP 1958981A JP S57135492 A JPS57135492 A JP S57135492A
Authority
JP
Japan
Prior art keywords
store buffer
data
address
stb
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56019589A
Other languages
Japanese (ja)
Inventor
Hideo Iyota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56019589A priority Critical patent/JPS57135492A/en
Publication of JPS57135492A publication Critical patent/JPS57135492A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Abstract

PURPOSE:To decrease the number of address comparators by changing control systems for a store buffer. CONSTITUTION:For fetching data from a main storage unit 1, when the bit 25 of a fetch address (FA) is a[1], eight addresses of a line address stack 7-0 are read and compared by an address comparator 12 with the bits 21-24 of the FA. Every time data is written in a bank 6-0, the counter value of an input point 10-0 goes up by one, and similarly every time data is written in a bank 6-1, the count value of a 10-1 goes up by one. When data is read out of a store buffer (STB), a priority level circuit 13 controls a selector SEL so that data stored in the STB earlier is outputted earlier.
JP56019589A 1981-02-14 1981-02-14 Control system for store buffer Pending JPS57135492A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56019589A JPS57135492A (en) 1981-02-14 1981-02-14 Control system for store buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56019589A JPS57135492A (en) 1981-02-14 1981-02-14 Control system for store buffer

Publications (1)

Publication Number Publication Date
JPS57135492A true JPS57135492A (en) 1982-08-21

Family

ID=12003434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56019589A Pending JPS57135492A (en) 1981-02-14 1981-02-14 Control system for store buffer

Country Status (1)

Country Link
JP (1) JPS57135492A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001053951A1 (en) * 2000-01-19 2001-07-26 Fujitsu Limited Memory control device and memory control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001053951A1 (en) * 2000-01-19 2001-07-26 Fujitsu Limited Memory control device and memory control method
US7093074B2 (en) 2000-01-19 2006-08-15 Fujitsu Limited Storage control device and storage control method

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