JPS5713513A - Information analysis device - Google Patents

Information analysis device

Info

Publication number
JPS5713513A
JPS5713513A JP8820680A JP8820680A JPS5713513A JP S5713513 A JPS5713513 A JP S5713513A JP 8820680 A JP8820680 A JP 8820680A JP 8820680 A JP8820680 A JP 8820680A JP S5713513 A JPS5713513 A JP S5713513A
Authority
JP
Japan
Prior art keywords
varied
circuit
stored
information
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8820680A
Other languages
Japanese (ja)
Inventor
Masayuki Tsutsumi
Tatsu Nakano
Junichi Inukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Signal Co Ltd
Original Assignee
Nippon Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority to JP8820680A priority Critical patent/JPS5713513A/en
Publication of JPS5713513A publication Critical patent/JPS5713513A/en
Pending legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor

Abstract

PURPOSE:To reduce a processing load to a CPU, by detecting and storing a varied bit from the present information and the previous information, and detecting and processing a varied bit of each kind, which requires an analysis by a mask pattern. CONSTITUTION:Display information EOR from a centralized traffic control device 1, and the previous information EOR are stored in a register RG3 and TG4, respectively. As for contents of RGs3,4, both the varied bits are detected by a varied information detecting circuit 5, and its result is stored un RG6. Contents of RG6 and a mask which is stored in RG7 are inputted to a varied information preparing circuit 8, both the varied bits of each kind are derected in said circuit, and its result is stored in RG9. As for contents of RG9, its varied direction is detected as to each kind by on and off variation detecting circuits 10, 11, and its result is stored by each kind in an address of RG12 according to an instruction from an address operating circuit 13. Each RG updates an address by a signal of an address updating circuit 14, and when an analysis is finished, contents of RG12 are sent to a CPU by a signal of an interruption generating circuit 15.
JP8820680A 1980-06-28 1980-06-28 Information analysis device Pending JPS5713513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8820680A JPS5713513A (en) 1980-06-28 1980-06-28 Information analysis device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8820680A JPS5713513A (en) 1980-06-28 1980-06-28 Information analysis device

Publications (1)

Publication Number Publication Date
JPS5713513A true JPS5713513A (en) 1982-01-23

Family

ID=13936420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8820680A Pending JPS5713513A (en) 1980-06-28 1980-06-28 Information analysis device

Country Status (1)

Country Link
JP (1) JPS5713513A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6063605A (en) * 1983-09-16 1985-04-12 Fanuc Ltd Numerical controller with composite skipping function
JPH01296312A (en) * 1988-05-24 1989-11-29 Shionogi & Co Ltd Device and method for debugging
JP2004115205A (en) * 2002-09-26 2004-04-15 Kirin Techno-System Corp Container excluding device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6063605A (en) * 1983-09-16 1985-04-12 Fanuc Ltd Numerical controller with composite skipping function
JPH01296312A (en) * 1988-05-24 1989-11-29 Shionogi & Co Ltd Device and method for debugging
JP2004115205A (en) * 2002-09-26 2004-04-15 Kirin Techno-System Corp Container excluding device

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