JPS57133769A - Noise eliminating circuit - Google Patents

Noise eliminating circuit

Info

Publication number
JPS57133769A
JPS57133769A JP56018005A JP1800581A JPS57133769A JP S57133769 A JPS57133769 A JP S57133769A JP 56018005 A JP56018005 A JP 56018005A JP 1800581 A JP1800581 A JP 1800581A JP S57133769 A JPS57133769 A JP S57133769A
Authority
JP
Japan
Prior art keywords
circuit
signal
count value
counter
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56018005A
Other languages
Japanese (ja)
Other versions
JPH0253988B2 (en
Inventor
Atsushi Oishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP56018005A priority Critical patent/JPS57133769A/en
Publication of JPS57133769A publication Critical patent/JPS57133769A/en
Publication of JPH0253988B2 publication Critical patent/JPH0253988B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40—Picture signal circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimile Transmission Control (AREA)
  • Facsimile Image Signal Circuits (AREA)
  • Image Processing (AREA)

Abstract

PURPOSE:To eliminate mixed noise and to pick up a required pulse signal only, by automatically setting a count value corresponding to the interval of a pulse signal to a storage means and introducing the pulse signal only with an interval corresponding to the count value. CONSTITUTION:The count value of a counter 8 is always outputted to a comparison circuit 9, and the count value of the counter 8 is set to a latch circuit 10 at the leading of an output signal of an output terminal Q2 of a pulse number detecting circuit 5. Since the counter 8 is reset only when a synchronizing signal is outputted from a synchronizing differentiation circuit 3 when a coincidence signal 1 is outputted from the circuit 9, only this synchronizing signal is transmitted from an AND circuit 4. Thus, even if a noise signal is inputted, a set signal is not inputted to AND circuit 6 via an OR circuit 14 from an FF11, then the counter 8 is not reset. A shift register 15 resets the count value of the circuit 10 when the number of dissidence is n.
JP56018005A 1981-02-12 1981-02-12 Noise eliminating circuit Granted JPS57133769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56018005A JPS57133769A (en) 1981-02-12 1981-02-12 Noise eliminating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56018005A JPS57133769A (en) 1981-02-12 1981-02-12 Noise eliminating circuit

Publications (2)

Publication Number Publication Date
JPS57133769A true JPS57133769A (en) 1982-08-18
JPH0253988B2 JPH0253988B2 (en) 1990-11-20

Family

ID=11959564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56018005A Granted JPS57133769A (en) 1981-02-12 1981-02-12 Noise eliminating circuit

Country Status (1)

Country Link
JP (1) JPS57133769A (en)

Also Published As

Publication number Publication date
JPH0253988B2 (en) 1990-11-20

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