JPS57132473A - Binary coding circuit for video signal - Google Patents
Binary coding circuit for video signalInfo
- Publication number
- JPS57132473A JPS57132473A JP56017816A JP1781681A JPS57132473A JP S57132473 A JPS57132473 A JP S57132473A JP 56017816 A JP56017816 A JP 56017816A JP 1781681 A JP1781681 A JP 1781681A JP S57132473 A JPS57132473 A JP S57132473A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- comparator
- output
- video signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
- H04N1/403—Discrimination between the two tones in the picture signal of a two-tone original
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Facsimile Image Signal Circuits (AREA)
- Image Input (AREA)
Abstract
PURPOSE:To achieve a comparison output with a threshold level following to the level of read-in pattern due to contrast by a pencil and the like, by combining a plurality of comparison circuits, peak hold circuit and addition circuits. CONSTITUTION:A video signal of read-in pattern is inputted to a comparator 2, peak holding circuits 4, 5 and an analog delay circuit 10. The comparator 2 binary-codes an input video signal by denoting a reference voltage generated at a threshold value generating circuit 1 as a threshold level and outputs it to a distributor 3. The output of the distributor 3 makes the circuit 4 effective between the 2n-1-th rise to the 2n-th rise of the pulse waveform of the output of the comparator 2, and makes the circuit 5 ineffective between the 2n-the and the 2n+1-th. The output of the circuits 4, 5 is added at an adder 7 and inputted to a proportional device 12, then a threshold signal is obtained from the device 12. On the other hand, a video signal delayed for a prescribed time at the circuit 10 is given to a comparator 11, where the signal is compared with the threshold signal obtained at the circuit 12, and the objective binary coded signal as the output of the comparator 11 is obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56017816A JPS57132473A (en) | 1981-02-09 | 1981-02-09 | Binary coding circuit for video signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56017816A JPS57132473A (en) | 1981-02-09 | 1981-02-09 | Binary coding circuit for video signal |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57132473A true JPS57132473A (en) | 1982-08-16 |
JPS6149872B2 JPS6149872B2 (en) | 1986-10-31 |
Family
ID=11954255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56017816A Granted JPS57132473A (en) | 1981-02-09 | 1981-02-09 | Binary coding circuit for video signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57132473A (en) |
-
1981
- 1981-02-09 JP JP56017816A patent/JPS57132473A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6149872B2 (en) | 1986-10-31 |
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