JPS57130457A - Mass assembling method of semiconductor device - Google Patents

Mass assembling method of semiconductor device

Info

Publication number
JPS57130457A
JPS57130457A JP1618281A JP1618281A JPS57130457A JP S57130457 A JPS57130457 A JP S57130457A JP 1618281 A JP1618281 A JP 1618281A JP 1618281 A JP1618281 A JP 1618281A JP S57130457 A JPS57130457 A JP S57130457A
Authority
JP
Japan
Prior art keywords
pattern
attached
copper foils
lead
perforated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1618281A
Other languages
Japanese (ja)
Other versions
JPS6217858B2 (en
Inventor
Yoshio Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP1618281A priority Critical patent/JPS57130457A/en
Priority to KR1019810005282A priority patent/KR850001541B1/en
Priority to GB8200313A priority patent/GB2093401B/en
Priority to DE3201133A priority patent/DE3201133A1/en
Publication of JPS57130457A publication Critical patent/JPS57130457A/en
Publication of JPS6217858B2 publication Critical patent/JPS6217858B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49534—Multi-layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable mass production and reduction in cost of a film carrier system device by a method wherein a film substrate is produced by two copper foils being attached by thermosetting resin, and a desired lead pattern on one of copper foils and a supporting pattern on another are provided. CONSTITUTION:Copper foils 11, 12 having a thickness around 35mum is attached to each other by an adhesive agent 13 of epoxy resin or the like having a thickness of approximately 30mum, and the film substrate 10 of a long length having a width for example of 5cm is fabricated. After index holes 14 are perforated at the both side of the substrate 10, a resist of desired shape is printed by screen printing, and a lead pattern 15 and a supporting pattern 21 are formed continuously and simultaneously using an etching device for both sides. By the pattern 21 perforated to form a ring by leaving the region which faces the bonding region on the pattern 15, a parasitic capacitance is reduced. In the assemblying process, after an element is fixed on a pad 16 on the pattern 15 and wire bonding is performed, a functional inspection may be performed if necessary. Subsequently an external terminal 23 is attached on a lead 18, and resin sealing is performed, and an independent device is separated by cutting a continuous pattern on both sides. By this method a continuous mass production process can be performed cheaply.
JP1618281A 1981-01-17 1981-02-04 Mass assembling method of semiconductor device Granted JPS57130457A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1618281A JPS57130457A (en) 1981-02-04 1981-02-04 Mass assembling method of semiconductor device
KR1019810005282A KR850001541B1 (en) 1981-01-17 1981-12-31 Composite film
GB8200313A GB2093401B (en) 1981-01-17 1982-01-06 Composite film
DE3201133A DE3201133A1 (en) 1981-01-17 1982-01-15 COMPOSITE LAYER ARRANGEMENT, IN PARTICULAR FOR USE IN A SEMICONDUCTOR ARRANGEMENT, AND METHOD FOR THE PRODUCTION THEREOF

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1618281A JPS57130457A (en) 1981-02-04 1981-02-04 Mass assembling method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57130457A true JPS57130457A (en) 1982-08-12
JPS6217858B2 JPS6217858B2 (en) 1987-04-20

Family

ID=11909368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1618281A Granted JPS57130457A (en) 1981-01-17 1981-02-04 Mass assembling method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57130457A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6235525A (en) * 1985-08-08 1987-02-16 Omron Tateisi Electronics Co Manufacture of hybrid integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5518068A (en) * 1978-07-26 1980-02-07 Citizen Watch Co Ltd Mount construction of semiconductor device
JPS5824954A (en) * 1981-08-06 1983-02-15 Fujitsu Ltd Address controlling system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5518068A (en) * 1978-07-26 1980-02-07 Citizen Watch Co Ltd Mount construction of semiconductor device
JPS5824954A (en) * 1981-08-06 1983-02-15 Fujitsu Ltd Address controlling system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6235525A (en) * 1985-08-08 1987-02-16 Omron Tateisi Electronics Co Manufacture of hybrid integrated circuit

Also Published As

Publication number Publication date
JPS6217858B2 (en) 1987-04-20

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