JPS57125363A - Test method of pll circuit - Google Patents

Test method of pll circuit

Info

Publication number
JPS57125363A
JPS57125363A JP56010963A JP1096381A JPS57125363A JP S57125363 A JPS57125363 A JP S57125363A JP 56010963 A JP56010963 A JP 56010963A JP 1096381 A JP1096381 A JP 1096381A JP S57125363 A JPS57125363 A JP S57125363A
Authority
JP
Japan
Prior art keywords
converter
lead
voltage
circuit
range
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56010963A
Other languages
Japanese (ja)
Other versions
JPH036468B2 (en
Inventor
Kazuo Saito
Masanori Tokunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP56010963A priority Critical patent/JPS57125363A/en
Publication of JPS57125363A publication Critical patent/JPS57125363A/en
Publication of JPH036468B2 publication Critical patent/JPH036468B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To test a lead-in range of a PLL circuit only through rough adjustment of a voltage control oscillator of a test circuit by a method wherein a pair of F/V converter and V/F converter matched in a PLL circuit composed of a voltage control oscillator and a phase detector is put in a loop including a test circuit. CONSTITUTION:An input signal change-over relay 8 is turned ''OFF'' and variable resistance 3 is adjusted to tune the oscillation frequency of a voltage control oscillator 2 to about 19KHz. The output of an F/V converter 11 at this time is memoried and held in a memory circuit 12 to become an input signal of one side of a summing-substracting operational unit 13. On the other hand, DC voltage defining a lead-in range of a PLL circuit to be impressed upon an input terminal 14 becomes the input signal of another of the operator 13. The output voltage of the operator 13 is applied to a V/F converter 15 to obtain the lead-in range measuring signal from the converter 15. Next the relay 8 is turned ''ON'' to measure the output voltage of the converter 11 by the output terminal 17 and to measure the input voltage of the converter 15 by the input terminal 16 for judging the lead-in range characteristic of the circuit to be tested to be good when both are on the same level.
JP56010963A 1981-01-27 1981-01-27 Test method of pll circuit Granted JPS57125363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56010963A JPS57125363A (en) 1981-01-27 1981-01-27 Test method of pll circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56010963A JPS57125363A (en) 1981-01-27 1981-01-27 Test method of pll circuit

Publications (2)

Publication Number Publication Date
JPS57125363A true JPS57125363A (en) 1982-08-04
JPH036468B2 JPH036468B2 (en) 1991-01-30

Family

ID=11764822

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56010963A Granted JPS57125363A (en) 1981-01-27 1981-01-27 Test method of pll circuit

Country Status (1)

Country Link
JP (1) JPS57125363A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260818A (en) * 1989-03-31 1990-10-23 Taiyo Yuden Co Ltd Method of adjusting phase locked loop circuit
CN105158604A (en) * 2015-08-25 2015-12-16 贵州航天计量测试技术研究所 QFN packaged phase-locked chip test device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02260818A (en) * 1989-03-31 1990-10-23 Taiyo Yuden Co Ltd Method of adjusting phase locked loop circuit
CN105158604A (en) * 2015-08-25 2015-12-16 贵州航天计量测试技术研究所 QFN packaged phase-locked chip test device

Also Published As

Publication number Publication date
JPH036468B2 (en) 1991-01-30

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