JPS57119518A - Rough quantization error amplifier - Google Patents
Rough quantization error amplifierInfo
- Publication number
- JPS57119518A JPS57119518A JP505481A JP505481A JPS57119518A JP S57119518 A JPS57119518 A JP S57119518A JP 505481 A JP505481 A JP 505481A JP 505481 A JP505481 A JP 505481A JP S57119518 A JPS57119518 A JP S57119518A
- Authority
- JP
- Japan
- Prior art keywords
- gain
- during
- point
- output
- switching pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
Abstract
PURPOSE:To enable a cascaded AD converter to perform high-speed, high-precision AD conversion by setting a gain low by a gain switching pulse during a period from an input point to an output point. CONSTITUTION:During a delay period from the input point of a sample holding analog signal to the output point of the DA-converted analog signal of the output signal of the 1st encoder 1 which encodes the high-order digit bits, an analog switch 8 is turned on by a gain switching pulse inputted from a terminal 10 to connect a resistance Rf2 to a feedback resistance Rf1 in parallel, thereby decreasing the gain of an amplifier 6. Therefore, the output signal is never in an overvoltage or overload state during the delay period, so a response speed is high and sufficient amplification is performed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP505481A JPS57119518A (en) | 1981-01-19 | 1981-01-19 | Rough quantization error amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP505481A JPS57119518A (en) | 1981-01-19 | 1981-01-19 | Rough quantization error amplifier |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57119518A true JPS57119518A (en) | 1982-07-26 |
JPH028494B2 JPH028494B2 (en) | 1990-02-26 |
Family
ID=11600678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP505481A Granted JPS57119518A (en) | 1981-01-19 | 1981-01-19 | Rough quantization error amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57119518A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51117862A (en) * | 1975-04-10 | 1976-10-16 | Nippon Hoso Kyokai <Nhk> | Vertically connected a/d converter |
-
1981
- 1981-01-19 JP JP505481A patent/JPS57119518A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51117862A (en) * | 1975-04-10 | 1976-10-16 | Nippon Hoso Kyokai <Nhk> | Vertically connected a/d converter |
Also Published As
Publication number | Publication date |
---|---|
JPH028494B2 (en) | 1990-02-26 |
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